1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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92 #
93 l1i_cache = L1Cache(size = options.l1i_size,
94 assoc = options.l1i_assoc,
95 start_index_bit = block_size_bits)
96 l1d_cache = L1Cache(size = options.l1d_size,
97 assoc = options.l1d_assoc,
98 start_index_bit = block_size_bits)
99
100 cpu_seq = RubySequencer(version = i,
101 icache = l1i_cache,
102 dcache = l1d_cache,
103 physMemPort = system.physmem.port,
104 physmem = system.physmem)
105
106 if piobus != None:
107 cpu_seq.pio_port = piobus.port
108
109 l1_cntrl = L1Cache_Controller(version = i,
110 cntrl_id = cntrl_count,
111 sequencer = cpu_seq,
112 L1IcacheMemory = l1i_cache,
113 L1DcacheMemory = l1d_cache,
114 l2_select_num_bits = l2_bits,
115 N_tokens = n_tokens,
116 retry_threshold = \
117 options.l1_retries,
118 fixed_timeout_latency = \
119 options.timeout_latency,
120 dynamic_timeout_enabled = \
121 not options.disable_dyn_timeouts,
122 no_mig_atomic = not \
123 options.allow_atomic_migration)
124
125 exec("system.l1_cntrl%d = l1_cntrl" % i)
126 #
127 # Add controllers and sequencers to the appropriate lists
128 #
129 cpu_sequencers.append(cpu_seq)
130 l1_cntrl_nodes.append(l1_cntrl)
131
132 cntrl_count += 1

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