1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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79
80 #
81 # Must create the individual controllers before the network to ensure the
82 # controller constructors are called before the network constructor
83 #
84 l2_bits = int(math.log(options.num_l2caches, 2))
85 block_size_bits = int(math.log(options.cacheline_size, 2))
86
87 for i in xrange(options.num_cpus):
88 #
89 # First create the Ruby objects associated with this cpu
90 #
91 l1i_cache = L1Cache(size = options.l1i_size,
92 assoc = options.l1i_assoc,
93 start_index_bit = block_size_bits)
94 l1d_cache = L1Cache(size = options.l1d_size,

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100 dcache = l1d_cache,
101 physMemPort = system.physmem.port,
102 physmem = system.physmem)
103
104 if piobus != None:
105 cpu_seq.pio_port = piobus.port
106
107 l1_cntrl = L1Cache_Controller(version = i,
108 sequencer = cpu_seq,
109 L1IcacheMemory = l1i_cache,
110 L1DcacheMemory = l1d_cache,
111 l2_select_num_bits = l2_bits,
112 N_tokens = n_tokens,
113 retry_threshold = \
114 options.l1_retries,
115 fixed_timeout_latency = \

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121
122 exec("system.l1_cntrl%d = l1_cntrl" % i)
123 #
124 # Add controllers and sequencers to the appropriate lists
125 #
126 cpu_sequencers.append(cpu_seq)
127 l1_cntrl_nodes.append(l1_cntrl)
128
129 l2_index_start = block_size_bits + l2_bits
130
131 for i in xrange(options.num_l2caches):
132 #
133 # First create the Ruby objects associated with this cpu
134 #
135 l2_cache = L2Cache(size = options.l2_size,
136 assoc = options.l2_assoc,
137 start_index_bit = l2_index_start)
138
139 l2_cntrl = L2Cache_Controller(version = i,
140 L2cacheMemory = l2_cache,
141 N_tokens = n_tokens)
142
143 exec("system.l2_cntrl%d = l2_cntrl" % i)
144 l2_cntrl_nodes.append(l2_cntrl)
145
146 phys_mem_size = long(system.physmem.range.second) - \
147 long(system.physmem.range.first) + 1
148 mem_module_size = phys_mem_size / options.num_dirs
149
150 for i in xrange(options.num_dirs):
151 #
152 # Create the Ruby objects associated with the directory controller
153 #
154
155 mem_cntrl = RubyMemoryControl(version = i)
156
157 dir_size = MemorySize('0B')
158 dir_size.value = mem_module_size
159
160 dir_cntrl = Directory_Controller(version = i,
161 directory = \
162 RubyDirectoryMemory(version = i,
163 size = \
164 dir_size),
165 memBuffer = mem_cntrl,
166 l2_select_num_bits = l2_bits)
167
168 exec("system.dir_cntrl%d = dir_cntrl" % i)
169 dir_cntrl_nodes.append(dir_cntrl)
170
171 for i, dma_device in enumerate(dma_devices):
172 #
173 # Create the Ruby objects associated with the dma controller
174 #
175 dma_seq = DMASequencer(version = i,
176 physMemPort = system.physmem.port,
177 physmem = system.physmem)
178
179 dma_cntrl = DMA_Controller(version = i,
180 dma_sequencer = dma_seq)
181
182 exec("system.dma_cntrl%d = dma_cntrl" % i)
183 if dma_device.type == 'MemTest':
184 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
185 else:
186 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
187 dma_cntrl_nodes.append(dma_cntrl)
188
189 all_cntrls = l1_cntrl_nodes + \
190 l2_cntrl_nodes + \
191 dir_cntrl_nodes + \
192 dma_cntrl_nodes
193
194 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)