1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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118 l1_cntrl.sequencer = cpu_seq
119 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
120
121 # Add controllers and sequencers to the appropriate lists
122 cpu_sequencers.append(cpu_seq)
123 l1_cntrl_nodes.append(l1_cntrl)
124
125 # Connect the L1 controllers and the network
126 l1_cntrl.requestFromL1Cache = ruby_system.network.slave
127 l1_cntrl.responseFromL1Cache = ruby_system.network.slave
128 l1_cntrl.persistentFromL1Cache = ruby_system.network.slave
129
130 l1_cntrl.requestToL1Cache = ruby_system.network.master
131 l1_cntrl.responseToL1Cache = ruby_system.network.master
132 l1_cntrl.persistentToL1Cache = ruby_system.network.master
133
134
135 l2_index_start = block_size_bits + l2_bits
136
137 for i in xrange(options.num_l2caches):
138 #
139 # First create the Ruby objects associated with this cpu
140 #

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147 N_tokens = n_tokens,
148 transitions_per_cycle = options.ports,
149 ruby_system = ruby_system)
150
151 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
152 l2_cntrl_nodes.append(l2_cntrl)
153
154 # Connect the L2 controllers and the network
155 l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
156 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
157 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
158
159 l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
160 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
161 l2_cntrl.responseToL2Cache = ruby_system.network.master
162 l2_cntrl.persistentToL2Cache = ruby_system.network.master
163
164
165 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
166 assert(phys_mem_size % options.num_dirs == 0)
167 mem_module_size = phys_mem_size / options.num_dirs
168
169 # Run each of the ruby memory controllers at a ratio of the frequency of
170 # the ruby system

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183 l2_select_num_bits = l2_bits,
184 transitions_per_cycle = options.ports,
185 ruby_system = ruby_system)
186
187 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
188 dir_cntrl_nodes.append(dir_cntrl)
189
190 # Connect the directory controllers and the network
191 dir_cntrl.requestToDir = ruby_system.network.master
192 dir_cntrl.responseToDir = ruby_system.network.master
193 dir_cntrl.persistentToDir = ruby_system.network.master
194 dir_cntrl.dmaRequestToDir = ruby_system.network.master
195
196 dir_cntrl.requestFromDir = ruby_system.network.slave
197 dir_cntrl.responseFromDir = ruby_system.network.slave
198 dir_cntrl.persistentFromDir = ruby_system.network.slave
199 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
200
201
202 for i, dma_port in enumerate(dma_ports):
203 #
204 # Create the Ruby objects associated with the dma controller
205 #
206 dma_seq = DMASequencer(version = i,
207 ruby_system = ruby_system,
208 slave = dma_port)
209
210 dma_cntrl = DMA_Controller(version = i,
211 dma_sequencer = dma_seq,
212 transitions_per_cycle = options.ports,
213 ruby_system = ruby_system)
214
215 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
216 dma_cntrl_nodes.append(dma_cntrl)
217
218 # Connect the dma controller to the network
219 dma_cntrl.responseFromDir = ruby_system.network.master
220 dma_cntrl.reqToDirectory = ruby_system.network.slave
221
222 all_cntrls = l1_cntrl_nodes + \
223 l2_cntrl_nodes + \
224 dir_cntrl_nodes + \
225 dma_cntrl_nodes
226
227 # Create the io controller and the sequencer
228 if full_system:
229 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
230 ruby_system._io_port = io_seq
231 io_controller = DMA_Controller(version = len(dma_ports),
232 dma_sequencer = io_seq,
233 ruby_system = ruby_system)
234 ruby_system.io_controller = io_controller
235
236 # Connect the dma controller to the network
237 io_controller.responseFromDir = ruby_system.network.master
238 io_controller.reqToDirectory = ruby_system.network.slave
239
240 all_cntrls = all_cntrls + [io_controller]
241
242
243 topology = create_topology(all_cntrls, options)
244 return (cpu_sequencers, dir_cntrl_nodes, topology)