1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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119 icache = l1i_cache,
120 dcache = l1d_cache,
121 clk_domain=system.cpu[i].clk_domain,
122 ruby_system = ruby_system)
123
124 l1_cntrl.sequencer = cpu_seq
125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
126
127 #
128 # Add controllers and sequencers to the appropriate lists
129 #
130 cpu_sequencers.append(cpu_seq)
131 l1_cntrl_nodes.append(l1_cntrl)
132
133 l2_index_start = block_size_bits + l2_bits
134
135 for i in xrange(options.num_l2caches):
136 #
137 # First create the Ruby objects associated with this cpu
138 #
139 l2_cache = L2Cache(size = options.l2_size,
140 assoc = options.l2_assoc,
141 start_index_bit = l2_index_start)
142
143 l2_cntrl = L2Cache_Controller(version = i,
144 L2cache = l2_cache,
145 N_tokens = n_tokens,
146 transitions_per_cycle = options.ports,
147 ruby_system = ruby_system)
148
149 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
150 l2_cntrl_nodes.append(l2_cntrl)
151
152 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
153 assert(phys_mem_size % options.num_dirs == 0)
154 mem_module_size = phys_mem_size / options.num_dirs
155
156 # Run each of the ruby memory controllers at a ratio of the frequency of
157 # the ruby system
158 # clk_divider value is a fix to pass regression.
159 ruby_system.memctrl_clk_domain = DerivedClockDomain(

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181 memBuffer = mem_cntrl,
182 l2_select_num_bits = l2_bits,
183 transitions_per_cycle = options.ports,
184 ruby_system = ruby_system)
185
186 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
187 dir_cntrl_nodes.append(dir_cntrl)
188
189 for i, dma_port in enumerate(dma_ports):
190 #
191 # Create the Ruby objects associated with the dma controller
192 #
193 dma_seq = DMASequencer(version = i,
194 ruby_system = ruby_system)
195
196 dma_cntrl = DMA_Controller(version = i,

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