1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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118 l1_cntrl.sequencer = cpu_seq
119 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
120
121 # Add controllers and sequencers to the appropriate lists
122 cpu_sequencers.append(cpu_seq)
123 l1_cntrl_nodes.append(l1_cntrl)
124
125 # Connect the L1 controllers and the network
126 l1_cntrl.requestFromL1Cache = MessageBuffer()
127 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
128 l1_cntrl.responseFromL1Cache = MessageBuffer()
129 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
130 l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True)
131 l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave
132
133 l1_cntrl.mandatoryQueue = MessageBuffer()
134 l1_cntrl.requestToL1Cache = MessageBuffer()
135 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
136 l1_cntrl.responseToL1Cache = MessageBuffer()
137 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
138 l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True)
139 l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master
140
141
142 l2_index_start = block_size_bits + l2_bits
143
144 for i in xrange(options.num_l2caches):
145 #
146 # First create the Ruby objects associated with this cpu
147 #

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154 N_tokens = n_tokens,
155 transitions_per_cycle = options.ports,
156 ruby_system = ruby_system)
157
158 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
159 l2_cntrl_nodes.append(l2_cntrl)
160
161 # Connect the L2 controllers and the network
162 l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
163 l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
164 l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
165 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
166 l2_cntrl.responseFromL2Cache = MessageBuffer()
167 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
168
169 l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
170 l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
171 l2_cntrl.L1RequestToL2Cache = MessageBuffer()
172 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
173 l2_cntrl.responseToL2Cache = MessageBuffer()
174 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
175 l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True)
176 l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master
177
178
179 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
180 assert(phys_mem_size % options.num_dirs == 0)
181 mem_module_size = phys_mem_size / options.num_dirs
182
183 # Run each of the ruby memory controllers at a ratio of the frequency of
184 # the ruby system

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197 l2_select_num_bits = l2_bits,
198 transitions_per_cycle = options.ports,
199 ruby_system = ruby_system)
200
201 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
202 dir_cntrl_nodes.append(dir_cntrl)
203
204 # Connect the directory controllers and the network
205 dir_cntrl.requestToDir = MessageBuffer()
206 dir_cntrl.requestToDir.slave = ruby_system.network.master
207 dir_cntrl.responseToDir = MessageBuffer()
208 dir_cntrl.responseToDir.slave = ruby_system.network.master
209 dir_cntrl.persistentToDir = MessageBuffer(ordered = True)
210 dir_cntrl.persistentToDir.slave = ruby_system.network.master
211 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
212 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
213
214 dir_cntrl.requestFromDir = MessageBuffer()
215 dir_cntrl.requestFromDir.master = ruby_system.network.slave
216 dir_cntrl.responseFromDir = MessageBuffer()
217 dir_cntrl.responseFromDir.master = ruby_system.network.slave
218 dir_cntrl.persistentFromDir = MessageBuffer(ordered = True)
219 dir_cntrl.persistentFromDir.master = ruby_system.network.slave
220 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
221 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
222 dir_cntrl.responseFromMemory = MessageBuffer()
223
224
225 for i, dma_port in enumerate(dma_ports):
226 #
227 # Create the Ruby objects associated with the dma controller
228 #
229 dma_seq = DMASequencer(version = i,
230 ruby_system = ruby_system,
231 slave = dma_port)
232
233 dma_cntrl = DMA_Controller(version = i,
234 dma_sequencer = dma_seq,
235 transitions_per_cycle = options.ports,
236 ruby_system = ruby_system)
237
238 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
239 dma_cntrl_nodes.append(dma_cntrl)
240
241 # Connect the dma controller to the network
242 dma_cntrl.mandatoryQueue = MessageBuffer()
243 dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
244 dma_cntrl.responseFromDir.slave = ruby_system.network.master
245 dma_cntrl.reqToDirectory = MessageBuffer()
246 dma_cntrl.reqToDirectory.master = ruby_system.network.slave
247
248 all_cntrls = l1_cntrl_nodes + \
249 l2_cntrl_nodes + \
250 dir_cntrl_nodes + \
251 dma_cntrl_nodes
252
253 # Create the io controller and the sequencer
254 if full_system:
255 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
256 ruby_system._io_port = io_seq
257 io_controller = DMA_Controller(version = len(dma_ports),
258 dma_sequencer = io_seq,
259 ruby_system = ruby_system)
260 ruby_system.io_controller = io_controller
261
262 # Connect the dma controller to the network
263 io_controller.mandatoryQueue = MessageBuffer()
264 io_controller.responseFromDir = MessageBuffer(ordered = True)
265 io_controller.responseFromDir.slave = ruby_system.network.master
266 io_controller.reqToDirectory = MessageBuffer()
267 io_controller.reqToDirectory.master = ruby_system.network.slave
268
269 all_cntrls = all_cntrls + [io_controller]
270
271
272 topology = create_topology(all_cntrls, options)
273 return (cpu_sequencers, dir_cntrl_nodes, topology)