MOESI_CMP_directory.py (9319:ab0a36d082bb) MOESI_CMP_directory.py (9468:721718c62859)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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101 dcache = l1d_cache,
102 ruby_system = ruby_system)
103
104 l1_cntrl.sequencer = cpu_seq
105
106 if piobus != None:
107 cpu_seq.pio_port = piobus.slave
108
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 92 unchanged lines hidden (view full) ---

101 dcache = l1d_cache,
102 ruby_system = ruby_system)
103
104 l1_cntrl.sequencer = cpu_seq
105
106 if piobus != None:
107 cpu_seq.pio_port = piobus.slave
108
109 exec("system.l1_cntrl%d = l1_cntrl" % i)
109 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
110 #
111 # Add controllers and sequencers to the appropriate lists
112 #
113 cpu_sequencers.append(cpu_seq)
114 l1_cntrl_nodes.append(l1_cntrl)
115
116 cntrl_count += 1
117

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125 assoc = options.l2_assoc,
126 start_index_bit = l2_index_start)
127
128 l2_cntrl = L2Cache_Controller(version = i,
129 cntrl_id = cntrl_count,
130 L2cacheMemory = l2_cache,
131 ruby_system = ruby_system)
132
110 #
111 # Add controllers and sequencers to the appropriate lists
112 #
113 cpu_sequencers.append(cpu_seq)
114 l1_cntrl_nodes.append(l1_cntrl)
115
116 cntrl_count += 1
117

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125 assoc = options.l2_assoc,
126 start_index_bit = l2_index_start)
127
128 l2_cntrl = L2Cache_Controller(version = i,
129 cntrl_id = cntrl_count,
130 L2cacheMemory = l2_cache,
131 ruby_system = ruby_system)
132
133 exec("system.l2_cntrl%d = l2_cntrl" % i)
133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 cntrl_count += 1
137
138 phys_mem_size = sum(map(lambda mem: mem.range.size(),
139 system.memories.unproxy(system)))
140 mem_module_size = phys_mem_size / options.num_dirs
141

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153 dir_cntrl = Directory_Controller(version = i,
154 cntrl_id = cntrl_count,
155 directory = \
156 RubyDirectoryMemory(version = i,
157 size = dir_size),
158 memBuffer = mem_cntrl,
159 ruby_system = ruby_system)
160
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 cntrl_count += 1
137
138 phys_mem_size = sum(map(lambda mem: mem.range.size(),
139 system.memories.unproxy(system)))
140 mem_module_size = phys_mem_size / options.num_dirs
141

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153 dir_cntrl = Directory_Controller(version = i,
154 cntrl_id = cntrl_count,
155 directory = \
156 RubyDirectoryMemory(version = i,
157 size = dir_size),
158 memBuffer = mem_cntrl,
159 ruby_system = ruby_system)
160
161 exec("system.dir_cntrl%d = dir_cntrl" % i)
161 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
162 dir_cntrl_nodes.append(dir_cntrl)
163
164 cntrl_count += 1
165
166 for i, dma_port in enumerate(dma_ports):
167 #
168 # Create the Ruby objects associated with the dma controller
169 #
170 dma_seq = DMASequencer(version = i,
171 ruby_system = ruby_system)
172
173 dma_cntrl = DMA_Controller(version = i,
174 cntrl_id = cntrl_count,
175 dma_sequencer = dma_seq,
176 ruby_system = ruby_system)
177
162 dir_cntrl_nodes.append(dir_cntrl)
163
164 cntrl_count += 1
165
166 for i, dma_port in enumerate(dma_ports):
167 #
168 # Create the Ruby objects associated with the dma controller
169 #
170 dma_seq = DMASequencer(version = i,
171 ruby_system = ruby_system)
172
173 dma_cntrl = DMA_Controller(version = i,
174 cntrl_id = cntrl_count,
175 dma_sequencer = dma_seq,
176 ruby_system = ruby_system)
177
178 exec("system.dma_cntrl%d = dma_cntrl" % i)
179 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
178 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
179 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
180 dma_cntrl_nodes.append(dma_cntrl)
181 cntrl_count += 1
182
183 all_cntrls = l1_cntrl_nodes + \
184 l2_cntrl_nodes + \
185 dir_cntrl_nodes + \
186 dma_cntrl_nodes
187
188 topology = create_topology(all_cntrls, options)
189
190 return (cpu_sequencers, dir_cntrl_nodes, topology)
180 dma_cntrl_nodes.append(dma_cntrl)
181 cntrl_count += 1
182
183 all_cntrls = l1_cntrl_nodes + \
184 l2_cntrl_nodes + \
185 dir_cntrl_nodes + \
186 dma_cntrl_nodes
187
188 topology = create_topology(all_cntrls, options)
189
190 return (cpu_sequencers, dir_cntrl_nodes, topology)