MOESI_CMP_directory.py (8923:820111f58fbb) MOESI_CMP_directory.py (8929:4148f9af0b70)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45 latency = 15
46
47def define_options(parser):
48 return
49
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 33 unchanged lines hidden (view full) ---

42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45 latency = 15
46
47def define_options(parser):
48 return
49
50def create_system(options, system, piobus, dma_devices, ruby_system):
50def create_system(options, system, piobus, dma_ports, ruby_system):
51
52 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
53 panic("This script requires the MOESI_CMP_directory protocol to be built.")
54
55 cpu_sequencers = []
56
57 #
58 # The ruby network creation expects the list of nodes in the system to be

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154 memBuffer = mem_cntrl,
155 ruby_system = ruby_system)
156
157 exec("system.dir_cntrl%d = dir_cntrl" % i)
158 dir_cntrl_nodes.append(dir_cntrl)
159
160 cntrl_count += 1
161
51
52 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
53 panic("This script requires the MOESI_CMP_directory protocol to be built.")
54
55 cpu_sequencers = []
56
57 #
58 # The ruby network creation expects the list of nodes in the system to be

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154 memBuffer = mem_cntrl,
155 ruby_system = ruby_system)
156
157 exec("system.dir_cntrl%d = dir_cntrl" % i)
158 dir_cntrl_nodes.append(dir_cntrl)
159
160 cntrl_count += 1
161
162 for i, dma_device in enumerate(dma_devices):
162 for i, dma_port in enumerate(dma_ports):
163 #
164 # Create the Ruby objects associated with the dma controller
165 #
166 dma_seq = DMASequencer(version = i,
167 ruby_system = ruby_system)
168
169 dma_cntrl = DMA_Controller(version = i,
170 cntrl_id = cntrl_count,
171 dma_sequencer = dma_seq,
172 ruby_system = ruby_system)
173
174 exec("system.dma_cntrl%d = dma_cntrl" % i)
163 #
164 # Create the Ruby objects associated with the dma controller
165 #
166 dma_seq = DMASequencer(version = i,
167 ruby_system = ruby_system)
168
169 dma_cntrl = DMA_Controller(version = i,
170 cntrl_id = cntrl_count,
171 dma_sequencer = dma_seq,
172 ruby_system = ruby_system)
173
174 exec("system.dma_cntrl%d = dma_cntrl" % i)
175 if dma_device.type == 'MemTest':
176 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
177 else:
178 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
175 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
179 dma_cntrl_nodes.append(dma_cntrl)
176 dma_cntrl_nodes.append(dma_cntrl)
180
181 cntrl_count += 1
182
183 all_cntrls = l1_cntrl_nodes + \
184 l2_cntrl_nodes + \
185 dir_cntrl_nodes + \
186 dma_cntrl_nodes
187
188 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
177 cntrl_count += 1
178
179 all_cntrls = l1_cntrl_nodes + \
180 l2_cntrl_nodes + \
181 dir_cntrl_nodes + \
182 dma_cntrl_nodes
183
184 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)