MOESI_CMP_directory.py (8436:5648986156db) | MOESI_CMP_directory.py (8477:4a6c166f61f7) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 151 unchanged lines hidden (view full) --- 160 cntrl_count += 1 161 162 for i, dma_device in enumerate(dma_devices): 163 # 164 # Create the Ruby objects associated with the dma controller 165 # 166 dma_seq = DMASequencer(version = i, 167 physMemPort = system.physmem.port, | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 151 unchanged lines hidden (view full) --- 160 cntrl_count += 1 161 162 for i, dma_device in enumerate(dma_devices): 163 # 164 # Create the Ruby objects associated with the dma controller 165 # 166 dma_seq = DMASequencer(version = i, 167 physMemPort = system.physmem.port, |
168 physmem = system.physmem) | 168 physmem = system.physmem, 169 ruby_system = ruby_system) |
169 170 dma_cntrl = DMA_Controller(version = i, 171 cntrl_id = cntrl_count, | 170 171 dma_cntrl = DMA_Controller(version = i, 172 cntrl_id = cntrl_count, |
172 dma_sequencer = dma_seq) | 173 dma_sequencer = dma_seq, 174 ruby_system = ruby_system) |
173 174 exec("system.dma_cntrl%d = dma_cntrl" % i) 175 if dma_device.type == 'MemTest': 176 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 177 else: 178 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 179 dma_cntrl_nodes.append(dma_cntrl) 180 181 cntrl_count += 1 182 183 all_cntrls = l1_cntrl_nodes + \ 184 l2_cntrl_nodes + \ 185 dir_cntrl_nodes + \ 186 dma_cntrl_nodes 187 188 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 175 176 exec("system.dma_cntrl%d = dma_cntrl" % i) 177 if dma_device.type == 'MemTest': 178 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 179 else: 180 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 181 dma_cntrl_nodes.append(dma_cntrl) 182 183 cntrl_count += 1 184 185 all_cntrls = l1_cntrl_nodes + \ 186 l2_cntrl_nodes + \ 187 dir_cntrl_nodes + \ 188 dma_cntrl_nodes 189 190 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |