MOESI_CMP_directory.py (8257:7226aebb77b4) MOESI_CMP_directory.py (8322:19949c6de823)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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79 #
80 l1i_cache = L1Cache(size = options.l1i_size,
81 assoc = options.l1i_assoc,
82 start_index_bit = block_size_bits)
83 l1d_cache = L1Cache(size = options.l1d_size,
84 assoc = options.l1d_assoc,
85 start_index_bit = block_size_bits)
86
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 70 unchanged lines hidden (view full) ---

79 #
80 l1i_cache = L1Cache(size = options.l1i_size,
81 assoc = options.l1i_assoc,
82 start_index_bit = block_size_bits)
83 l1d_cache = L1Cache(size = options.l1d_size,
84 assoc = options.l1d_assoc,
85 start_index_bit = block_size_bits)
86
87 l1_cntrl = L1Cache_Controller(version = i,
88 cntrl_id = cntrl_count,
89 L1IcacheMemory = l1i_cache,
90 L1DcacheMemory = l1d_cache,
91 l2_select_num_bits = l2_bits)
92
87 cpu_seq = RubySequencer(version = i,
88 icache = l1i_cache,
89 dcache = l1d_cache,
90 physMemPort = system.physmem.port,
91 physmem = system.physmem)
92
93 cpu_seq = RubySequencer(version = i,
94 icache = l1i_cache,
95 dcache = l1d_cache,
96 physMemPort = system.physmem.port,
97 physmem = system.physmem)
98
99 l1_cntrl.sequencer = cpu_seq
100
93 if piobus != None:
94 cpu_seq.pio_port = piobus.port
95
101 if piobus != None:
102 cpu_seq.pio_port = piobus.port
103
96 l1_cntrl = L1Cache_Controller(version = i,
97 cntrl_id = cntrl_count,
98 sequencer = cpu_seq,
99 L1IcacheMemory = l1i_cache,
100 L1DcacheMemory = l1d_cache,
101 l2_select_num_bits = l2_bits)
102
103 exec("system.l1_cntrl%d = l1_cntrl" % i)
104 #
105 # Add controllers and sequencers to the appropriate lists
106 #
107 cpu_sequencers.append(cpu_seq)
108 l1_cntrl_nodes.append(l1_cntrl)
109
110 cntrl_count += 1

--- 74 unchanged lines hidden --- 		104 exec("system.l1_cntrl%d = l1_cntrl" % i)
105 #
106 # Add controllers and sequencers to the appropriate lists
107 #
108 cpu_sequencers.append(cpu_seq)
109 l1_cntrl_nodes.append(l1_cntrl)
110
111 cntrl_count += 1

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