MOESI_CMP_directory.py (8180:d8587c913ccf) | MOESI_CMP_directory.py (8257:7226aebb77b4) |
---|---|
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 56 unchanged lines hidden (view full) --- 65 dma_cntrl_nodes = [] 66 67 # 68 # Must create the individual controllers before the network to ensure the 69 # controller constructors are called before the network constructor 70 # 71 l2_bits = int(math.log(options.num_l2caches, 2)) 72 block_size_bits = int(math.log(options.cacheline_size, 2)) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 56 unchanged lines hidden (view full) --- 65 dma_cntrl_nodes = [] 66 67 # 68 # Must create the individual controllers before the network to ensure the 69 # controller constructors are called before the network constructor 70 # 71 l2_bits = int(math.log(options.num_l2caches, 2)) 72 block_size_bits = int(math.log(options.cacheline_size, 2)) |
73 74 cntrl_count = 0 |
|
73 74 for i in xrange(options.num_cpus): 75 # 76 # First create the Ruby objects associated with this cpu 77 # 78 l1i_cache = L1Cache(size = options.l1i_size, 79 assoc = options.l1i_assoc, 80 start_index_bit = block_size_bits) --- 6 unchanged lines hidden (view full) --- 87 dcache = l1d_cache, 88 physMemPort = system.physmem.port, 89 physmem = system.physmem) 90 91 if piobus != None: 92 cpu_seq.pio_port = piobus.port 93 94 l1_cntrl = L1Cache_Controller(version = i, | 75 76 for i in xrange(options.num_cpus): 77 # 78 # First create the Ruby objects associated with this cpu 79 # 80 l1i_cache = L1Cache(size = options.l1i_size, 81 assoc = options.l1i_assoc, 82 start_index_bit = block_size_bits) --- 6 unchanged lines hidden (view full) --- 89 dcache = l1d_cache, 90 physMemPort = system.physmem.port, 91 physmem = system.physmem) 92 93 if piobus != None: 94 cpu_seq.pio_port = piobus.port 95 96 l1_cntrl = L1Cache_Controller(version = i, |
97 cntrl_id = cntrl_count, |
|
95 sequencer = cpu_seq, 96 L1IcacheMemory = l1i_cache, 97 L1DcacheMemory = l1d_cache, 98 l2_select_num_bits = l2_bits) 99 100 exec("system.l1_cntrl%d = l1_cntrl" % i) 101 # 102 # Add controllers and sequencers to the appropriate lists 103 # 104 cpu_sequencers.append(cpu_seq) 105 l1_cntrl_nodes.append(l1_cntrl) 106 | 98 sequencer = cpu_seq, 99 L1IcacheMemory = l1i_cache, 100 L1DcacheMemory = l1d_cache, 101 l2_select_num_bits = l2_bits) 102 103 exec("system.l1_cntrl%d = l1_cntrl" % i) 104 # 105 # Add controllers and sequencers to the appropriate lists 106 # 107 cpu_sequencers.append(cpu_seq) 108 l1_cntrl_nodes.append(l1_cntrl) 109 |
110 cntrl_count += 1 111 |
|
107 l2_index_start = block_size_bits + l2_bits 108 109 for i in xrange(options.num_l2caches): 110 # 111 # First create the Ruby objects associated with this cpu 112 # 113 l2_cache = L2Cache(size = options.l2_size, 114 assoc = options.l2_assoc, 115 start_index_bit = l2_index_start) 116 117 l2_cntrl = L2Cache_Controller(version = i, | 112 l2_index_start = block_size_bits + l2_bits 113 114 for i in xrange(options.num_l2caches): 115 # 116 # First create the Ruby objects associated with this cpu 117 # 118 l2_cache = L2Cache(size = options.l2_size, 119 assoc = options.l2_assoc, 120 start_index_bit = l2_index_start) 121 122 l2_cntrl = L2Cache_Controller(version = i, |
123 cntrl_id = cntrl_count, |
|
118 L2cacheMemory = l2_cache) 119 120 exec("system.l2_cntrl%d = l2_cntrl" % i) 121 l2_cntrl_nodes.append(l2_cntrl) | 124 L2cacheMemory = l2_cache) 125 126 exec("system.l2_cntrl%d = l2_cntrl" % i) 127 l2_cntrl_nodes.append(l2_cntrl) |
128 129 cntrl_count += 1 |
|
122 123 phys_mem_size = long(system.physmem.range.second) - \ 124 long(system.physmem.range.first) + 1 125 mem_module_size = phys_mem_size / options.num_dirs 126 127 for i in xrange(options.num_dirs): 128 # 129 # Create the Ruby objects associated with the directory controller 130 # 131 132 mem_cntrl = RubyMemoryControl(version = i) 133 134 dir_size = MemorySize('0B') 135 dir_size.value = mem_module_size 136 137 dir_cntrl = Directory_Controller(version = i, | 130 131 phys_mem_size = long(system.physmem.range.second) - \ 132 long(system.physmem.range.first) + 1 133 mem_module_size = phys_mem_size / options.num_dirs 134 135 for i in xrange(options.num_dirs): 136 # 137 # Create the Ruby objects associated with the directory controller 138 # 139 140 mem_cntrl = RubyMemoryControl(version = i) 141 142 dir_size = MemorySize('0B') 143 dir_size.value = mem_module_size 144 145 dir_cntrl = Directory_Controller(version = i, |
146 cntrl_id = cntrl_count, |
|
138 directory = \ 139 RubyDirectoryMemory(version = i, 140 size = \ 141 dir_size), 142 memBuffer = mem_cntrl) 143 144 exec("system.dir_cntrl%d = dir_cntrl" % i) 145 dir_cntrl_nodes.append(dir_cntrl) 146 | 147 directory = \ 148 RubyDirectoryMemory(version = i, 149 size = \ 150 dir_size), 151 memBuffer = mem_cntrl) 152 153 exec("system.dir_cntrl%d = dir_cntrl" % i) 154 dir_cntrl_nodes.append(dir_cntrl) 155 |
156 cntrl_count += 1 157 |
|
147 for i, dma_device in enumerate(dma_devices): 148 # 149 # Create the Ruby objects associated with the dma controller 150 # 151 dma_seq = DMASequencer(version = i, 152 physMemPort = system.physmem.port, 153 physmem = system.physmem) 154 155 dma_cntrl = DMA_Controller(version = i, | 158 for i, dma_device in enumerate(dma_devices): 159 # 160 # Create the Ruby objects associated with the dma controller 161 # 162 dma_seq = DMASequencer(version = i, 163 physMemPort = system.physmem.port, 164 physmem = system.physmem) 165 166 dma_cntrl = DMA_Controller(version = i, |
167 cntrl_id = cntrl_count, |
|
156 dma_sequencer = dma_seq) 157 158 exec("system.dma_cntrl%d = dma_cntrl" % i) 159 if dma_device.type == 'MemTest': 160 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 161 else: 162 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 163 dma_cntrl_nodes.append(dma_cntrl) 164 | 168 dma_sequencer = dma_seq) 169 170 exec("system.dma_cntrl%d = dma_cntrl" % i) 171 if dma_device.type == 'MemTest': 172 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 173 else: 174 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 175 dma_cntrl_nodes.append(dma_cntrl) 176 |
177 cntrl_count += 1 178 |
|
165 all_cntrls = l1_cntrl_nodes + \ 166 l2_cntrl_nodes + \ 167 dir_cntrl_nodes + \ 168 dma_cntrl_nodes 169 170 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 179 all_cntrls = l1_cntrl_nodes + \ 180 l2_cntrl_nodes + \ 181 dir_cntrl_nodes + \ 182 dma_cntrl_nodes 183 184 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |