MOESI_CMP_directory.py (7633:d8112aa18a1b) MOESI_CMP_directory.py (8180:d8587c913ccf)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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63 l2_cntrl_nodes = []
64 dir_cntrl_nodes = []
65 dma_cntrl_nodes = []
66
67 #
68 # Must create the individual controllers before the network to ensure the
69 # controller constructors are called before the network constructor
70 #
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 54 unchanged lines hidden (view full) ---

63 l2_cntrl_nodes = []
64 dir_cntrl_nodes = []
65 dma_cntrl_nodes = []
66
67 #
68 # Must create the individual controllers before the network to ensure the
69 # controller constructors are called before the network constructor
70 #
71 l2_bits = int(math.log(options.num_l2caches, 2))
72 block_size_bits = int(math.log(options.cacheline_size, 2))
71
72 for i in xrange(options.num_cpus):
73 #
74 # First create the Ruby objects associated with this cpu
75 #
76 l1i_cache = L1Cache(size = options.l1i_size,
73
74 for i in xrange(options.num_cpus):
75 #
76 # First create the Ruby objects associated with this cpu
77 #
78 l1i_cache = L1Cache(size = options.l1i_size,
77 assoc = options.l1i_assoc)
79 assoc = options.l1i_assoc,
80 start_index_bit = block_size_bits)
78 l1d_cache = L1Cache(size = options.l1d_size,
81 l1d_cache = L1Cache(size = options.l1d_size,
79 assoc = options.l1d_assoc)
82 assoc = options.l1d_assoc,
83 start_index_bit = block_size_bits)
80
81 cpu_seq = RubySequencer(version = i,
82 icache = l1i_cache,
83 dcache = l1d_cache,
84 physMemPort = system.physmem.port,
85 physmem = system.physmem)
86
87 if piobus != None:
88 cpu_seq.pio_port = piobus.port
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 sequencer = cpu_seq,
92 L1IcacheMemory = l1i_cache,
93 L1DcacheMemory = l1d_cache,
84
85 cpu_seq = RubySequencer(version = i,
86 icache = l1i_cache,
87 dcache = l1d_cache,
88 physMemPort = system.physmem.port,
89 physmem = system.physmem)
90
91 if piobus != None:
92 cpu_seq.pio_port = piobus.port
93
94 l1_cntrl = L1Cache_Controller(version = i,
95 sequencer = cpu_seq,
96 L1IcacheMemory = l1i_cache,
97 L1DcacheMemory = l1d_cache,
94 l2_select_num_bits = \
95 math.log(options.num_l2caches,
96 2))
98 l2_select_num_bits = l2_bits)
97
98 exec("system.l1_cntrl%d = l1_cntrl" % i)
99 #
100 # Add controllers and sequencers to the appropriate lists
101 #
102 cpu_sequencers.append(cpu_seq)
103 l1_cntrl_nodes.append(l1_cntrl)
104
99
100 exec("system.l1_cntrl%d = l1_cntrl" % i)
101 #
102 # Add controllers and sequencers to the appropriate lists
103 #
104 cpu_sequencers.append(cpu_seq)
105 l1_cntrl_nodes.append(l1_cntrl)
106
107 l2_index_start = block_size_bits + l2_bits
108
105 for i in xrange(options.num_l2caches):
106 #
107 # First create the Ruby objects associated with this cpu
108 #
109 l2_cache = L2Cache(size = options.l2_size,
109 for i in xrange(options.num_l2caches):
110 #
111 # First create the Ruby objects associated with this cpu
112 #
113 l2_cache = L2Cache(size = options.l2_size,
110 assoc = options.l2_assoc)
114 assoc = options.l2_assoc,
115 start_index_bit = l2_index_start)
111
112 l2_cntrl = L2Cache_Controller(version = i,
113 L2cacheMemory = l2_cache)
114
115 exec("system.l2_cntrl%d = l2_cntrl" % i)
116 l2_cntrl_nodes.append(l2_cntrl)
117
118 phys_mem_size = long(system.physmem.range.second) - \

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117 l2_cntrl = L2Cache_Controller(version = i,
118 L2cacheMemory = l2_cache)
119
120 exec("system.l2_cntrl%d = l2_cntrl" % i)
121 l2_cntrl_nodes.append(l2_cntrl)
122
123 phys_mem_size = long(system.physmem.range.second) - \

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