MOESI_CMP_directory.py (7544:90c5eb6a5e66) MOESI_CMP_directory.py (7633:d8112aa18a1b)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 138 unchanged lines hidden (view full) ---

147 physMemPort = system.physmem.port,
148 physmem = system.physmem)
149
150 dma_cntrl = DMA_Controller(version = i,
151 dma_sequencer = dma_seq)
152
153 exec("system.dma_cntrl%d = dma_cntrl" % i)
154 if dma_device.type == 'MemTest':
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 138 unchanged lines hidden (view full) ---

147 physMemPort = system.physmem.port,
148 physmem = system.physmem)
149
150 dma_cntrl = DMA_Controller(version = i,
151 dma_sequencer = dma_seq)
152
153 exec("system.dma_cntrl%d = dma_cntrl" % i)
154 if dma_device.type == 'MemTest':
155 system.dma_cntrl.dma_sequencer.port = dma_device.test
155 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
156 else:
156 else:
157 system.dma_cntrl.dma_sequencer.port = dma_device.dma
158 dma_cntrl.dma_sequencer.port = dma_device.dma
157 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
159 dma_cntrl_nodes.append(dma_cntrl)
160
161 all_cntrls = l1_cntrl_nodes + \
162 l2_cntrl_nodes + \
163 dir_cntrl_nodes + \
164 dma_cntrl_nodes
165
166 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
158 dma_cntrl_nodes.append(dma_cntrl)
159
160 all_cntrls = l1_cntrl_nodes + \
161 l2_cntrl_nodes + \
162 dir_cntrl_nodes + \
163 dma_cntrl_nodes
164
165 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)