MOESI_CMP_directory.py (6911:1fdbff869ff4) MOESI_CMP_directory.py (7015:6c91d41dfc12)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 62 unchanged lines hidden (view full) ---

71 #
72 # First create the Ruby objects associated with this cpu
73 #
74 l1i_cache = L1Cache(size = options.l1i_size,
75 assoc = options.l1i_assoc)
76 l1d_cache = L1Cache(size = options.l1d_size,
77 assoc = options.l1d_assoc)
78
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 62 unchanged lines hidden (view full) ---

71 #
72 # First create the Ruby objects associated with this cpu
73 #
74 l1i_cache = L1Cache(size = options.l1i_size,
75 assoc = options.l1i_assoc)
76 l1d_cache = L1Cache(size = options.l1d_size,
77 assoc = options.l1d_assoc)
78
79 cpu_seq = RubySequencer(icache = l1i_cache,
79 cpu_seq = RubySequencer(version = i,
80 icache = l1i_cache,
80 dcache = l1d_cache,
81 physMemPort = phys_mem.port,
82 physmem = phys_mem)
83
84 if piobus != None:
85 cpu_seq.pio_port = piobus.port
86
87 l1_cntrl = L1Cache_Controller(version = i,

--- 64 unchanged lines hidden --- 		81 dcache = l1d_cache,
82 physMemPort = phys_mem.port,
83 physmem = phys_mem)
84
85 if piobus != None:
86 cpu_seq.pio_port = piobus.port
87
88 l1_cntrl = L1Cache_Controller(version = i,

--- 64 unchanged lines hidden ---