MOESI_CMP_directory.py (12976:125099a94768) MOESI_CMP_directory.py (13731:67cd980cb20f)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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62
63 #
64 # Must create the individual controllers before the network to ensure the
65 # controller constructors are called before the network constructor
66 #
67 l2_bits = int(math.log(options.num_l2caches, 2))
68 block_size_bits = int(math.log(options.cacheline_size, 2))
69
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 53 unchanged lines hidden (view full) ---

62
63 #
64 # Must create the individual controllers before the network to ensure the
65 # controller constructors are called before the network constructor
66 #
67 l2_bits = int(math.log(options.num_l2caches, 2))
68 block_size_bits = int(math.log(options.cacheline_size, 2))
69
70 for i in xrange(options.num_cpus):
70 for i in range(options.num_cpus):
71 #
72 # First create the Ruby objects associated with this cpu
73 #
74 l1i_cache = L1Cache(size = options.l1i_size,
75 assoc = options.l1i_assoc,
76 start_index_bit = block_size_bits,
77 is_icache = True)
78 l1d_cache = L1Cache(size = options.l1d_size,

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121 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
122 l1_cntrl.responseToL1Cache = MessageBuffer()
123 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
124 l1_cntrl.triggerQueue = MessageBuffer(ordered = True)
125
126
127 l2_index_start = block_size_bits + l2_bits
128
71 #
72 # First create the Ruby objects associated with this cpu
73 #
74 l1i_cache = L1Cache(size = options.l1i_size,
75 assoc = options.l1i_assoc,
76 start_index_bit = block_size_bits,
77 is_icache = True)
78 l1d_cache = L1Cache(size = options.l1d_size,

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121 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
122 l1_cntrl.responseToL1Cache = MessageBuffer()
123 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
124 l1_cntrl.triggerQueue = MessageBuffer(ordered = True)
125
126
127 l2_index_start = block_size_bits + l2_bits
128
129 for i in xrange(options.num_l2caches):
129 for i in range(options.num_l2caches):
130 #
131 # First create the Ruby objects associated with this cpu
132 #
133 l2_cache = L2Cache(size = options.l2_size,
134 assoc = options.l2_assoc,
135 start_index_bit = l2_index_start)
136
137 l2_cntrl = L2Cache_Controller(version = i,

--- 106 unchanged lines hidden --- 		130 #
131 # First create the Ruby objects associated with this cpu
132 #
133 l2_cache = L2Cache(size = options.l2_size,
134 assoc = options.l2_assoc,
135 start_index_bit = l2_index_start)
136
137 l2_cntrl = L2Cache_Controller(version = i,

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