MOESI_CMP_directory.py (10300:ed3816dae6d5) | MOESI_CMP_directory.py (10311:ad9c042dce54) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 90 unchanged lines hidden (view full) --- 99 icache = l1i_cache, 100 dcache = l1d_cache, 101 clk_domain=system.cpu[i].clk_domain, 102 ruby_system = ruby_system) 103 104 l1_cntrl.sequencer = cpu_seq 105 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 106 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 90 unchanged lines hidden (view full) --- 99 icache = l1i_cache, 100 dcache = l1d_cache, 101 clk_domain=system.cpu[i].clk_domain, 102 ruby_system = ruby_system) 103 104 l1_cntrl.sequencer = cpu_seq 105 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 106 |
107 # | |
108 # Add controllers and sequencers to the appropriate lists | 107 # Add controllers and sequencers to the appropriate lists |
109 # | |
110 cpu_sequencers.append(cpu_seq) 111 l1_cntrl_nodes.append(l1_cntrl) 112 | 108 cpu_sequencers.append(cpu_seq) 109 l1_cntrl_nodes.append(l1_cntrl) 110 |
111 # Connect the L1 controllers and the network 112 l1_cntrl.requestFromL1Cache = ruby_system.network.slave 113 l1_cntrl.responseFromL1Cache = ruby_system.network.slave 114 l1_cntrl.requestToL1Cache = ruby_system.network.master 115 l1_cntrl.responseToL1Cache = ruby_system.network.master 116 117 |
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113 l2_index_start = block_size_bits + l2_bits 114 115 for i in xrange(options.num_l2caches): 116 # 117 # First create the Ruby objects associated with this cpu 118 # 119 l2_cache = L2Cache(size = options.l2_size, 120 assoc = options.l2_assoc, 121 start_index_bit = l2_index_start) 122 123 l2_cntrl = L2Cache_Controller(version = i, 124 L2cache = l2_cache, 125 transitions_per_cycle = options.ports, 126 ruby_system = ruby_system) 127 128 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 129 l2_cntrl_nodes.append(l2_cntrl) 130 | 118 l2_index_start = block_size_bits + l2_bits 119 120 for i in xrange(options.num_l2caches): 121 # 122 # First create the Ruby objects associated with this cpu 123 # 124 l2_cache = L2Cache(size = options.l2_size, 125 assoc = options.l2_assoc, 126 start_index_bit = l2_index_start) 127 128 l2_cntrl = L2Cache_Controller(version = i, 129 L2cache = l2_cache, 130 transitions_per_cycle = options.ports, 131 ruby_system = ruby_system) 132 133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 134 l2_cntrl_nodes.append(l2_cntrl) 135 |
136 # Connect the L2 controllers and the network 137 l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave 138 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 139 l2_cntrl.responseFromL2Cache = ruby_system.network.slave 140 141 l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master 142 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 143 l2_cntrl.responseToL2Cache = ruby_system.network.master 144 145 |
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131 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 132 assert(phys_mem_size % options.num_dirs == 0) 133 mem_module_size = phys_mem_size / options.num_dirs 134 | 146 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 147 assert(phys_mem_size % options.num_dirs == 0) 148 mem_module_size = phys_mem_size / options.num_dirs 149 |
150 |
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135 # Run each of the ruby memory controllers at a ratio of the frequency of 136 # the ruby system. 137 # clk_divider value is a fix to pass regression. 138 ruby_system.memctrl_clk_domain = DerivedClockDomain( 139 clk_domain=ruby_system.clk_domain, 140 clk_divider=3) 141 142 for i in xrange(options.num_dirs): --- 16 unchanged lines hidden (view full) --- 159 use_map = options.use_map), 160 memBuffer = mem_cntrl, 161 transitions_per_cycle = options.ports, 162 ruby_system = ruby_system) 163 164 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 165 dir_cntrl_nodes.append(dir_cntrl) 166 | 151 # Run each of the ruby memory controllers at a ratio of the frequency of 152 # the ruby system. 153 # clk_divider value is a fix to pass regression. 154 ruby_system.memctrl_clk_domain = DerivedClockDomain( 155 clk_domain=ruby_system.clk_domain, 156 clk_divider=3) 157 158 for i in xrange(options.num_dirs): --- 16 unchanged lines hidden (view full) --- 175 use_map = options.use_map), 176 memBuffer = mem_cntrl, 177 transitions_per_cycle = options.ports, 178 ruby_system = ruby_system) 179 180 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 181 dir_cntrl_nodes.append(dir_cntrl) 182 |
183 # Connect the directory controllers and the network 184 dir_cntrl.requestToDir = ruby_system.network.master 185 dir_cntrl.responseToDir = ruby_system.network.master 186 dir_cntrl.responseFromDir = ruby_system.network.slave 187 dir_cntrl.forwardFromDir = ruby_system.network.slave 188 189 |
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167 for i, dma_port in enumerate(dma_ports): 168 # 169 # Create the Ruby objects associated with the dma controller 170 # 171 dma_seq = DMASequencer(version = i, 172 ruby_system = ruby_system) 173 174 dma_cntrl = DMA_Controller(version = i, 175 dma_sequencer = dma_seq, 176 transitions_per_cycle = options.ports, 177 ruby_system = ruby_system) 178 179 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 180 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 181 dma_cntrl_nodes.append(dma_cntrl) 182 | 190 for i, dma_port in enumerate(dma_ports): 191 # 192 # Create the Ruby objects associated with the dma controller 193 # 194 dma_seq = DMASequencer(version = i, 195 ruby_system = ruby_system) 196 197 dma_cntrl = DMA_Controller(version = i, 198 dma_sequencer = dma_seq, 199 transitions_per_cycle = options.ports, 200 ruby_system = ruby_system) 201 202 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 203 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 204 dma_cntrl_nodes.append(dma_cntrl) 205 |
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183 all_cntrls = l1_cntrl_nodes + \ 184 l2_cntrl_nodes + \ 185 dir_cntrl_nodes + \ 186 dma_cntrl_nodes 187 188 topology = create_topology(all_cntrls, options) | 207 all_cntrls = l1_cntrl_nodes + \ 208 l2_cntrl_nodes + \ 209 dir_cntrl_nodes + \ 210 dma_cntrl_nodes 211 212 topology = create_topology(all_cntrls, options) |
189 | |
190 return (cpu_sequencers, dir_cntrl_nodes, topology) | 213 return (cpu_sequencers, dir_cntrl_nodes, topology) |