1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 66 unchanged lines hidden (view full) --- 75 cntrl_count = 0 76 77 for i in xrange(options.num_cpus): 78 # 79 # First create the Ruby objects associated with this cpu 80 # 81 l1i_cache = L1Cache(size = options.l1i_size, 82 assoc = options.l1i_assoc, |
83 start_index_bit = block_size_bits, 84 is_icache = True) |
85 l1d_cache = L1Cache(size = options.l1d_size, 86 assoc = options.l1d_assoc, |
87 start_index_bit = block_size_bits, 88 is_icache = False) |
89 90 l1_cntrl = L1Cache_Controller(version = i, 91 cntrl_id = cntrl_count, 92 L1IcacheMemory = l1i_cache, 93 L1DcacheMemory = l1d_cache, 94 l2_select_num_bits = l2_bits, 95 send_evictions = ( 96 options.cpu_type == "detailed"), --- 94 unchanged lines hidden --- |