1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 142 unchanged lines hidden (view full) --- 151 # Run each of the ruby memory controllers at a ratio of the frequency of 152 # the ruby system. 153 # clk_divider value is a fix to pass regression. 154 ruby_system.memctrl_clk_domain = DerivedClockDomain( 155 clk_domain=ruby_system.clk_domain, 156 clk_divider=3) 157 158 for i in xrange(options.num_dirs): |
159 dir_size = MemorySize('0B') 160 dir_size.value = mem_module_size 161 162 dir_cntrl = Directory_Controller(version = i, |
163 directory = RubyDirectoryMemory( 164 version = i, size = dir_size), |
165 transitions_per_cycle = options.ports, 166 ruby_system = ruby_system) 167 168 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 169 dir_cntrl_nodes.append(dir_cntrl) 170 171 # Connect the directory controllers and the network 172 dir_cntrl.requestToDir = ruby_system.network.master --- 51 unchanged lines hidden --- |