1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 78 unchanged lines hidden (view full) --- 87 88 l1_cntrl = L1Cache_Controller(version = i, 89 L1Icache = l1i_cache, 90 L1Dcache = l1d_cache, 91 l2_select_num_bits = l2_bits, 92 send_evictions = ( 93 options.cpu_type == "detailed"), 94 transitions_per_cycle = options.ports, |
95 clk_domain=system.cpu[i].clk_domain, |
96 ruby_system = ruby_system) 97 98 cpu_seq = RubySequencer(version = i, 99 icache = l1i_cache, 100 dcache = l1d_cache, |
101 clk_domain=system.cpu[i].clk_domain, |
102 ruby_system = ruby_system) 103 104 l1_cntrl.sequencer = cpu_seq 105 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 106 107 # 108 # Add controllers and sequencers to the appropriate lists 109 # --- 81 unchanged lines hidden --- |