1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 88 unchanged lines hidden (view full) --- 97 cpu_seq = RubySequencer(version = i, 98 icache = l1i_cache, 99 dcache = l1d_cache, 100 ruby_system = ruby_system) 101 102 l1_cntrl.sequencer = cpu_seq 103 104 if piobus != None: |
105 cpu_seq.pio_master_port = piobus.slave 106 cpu_seq.mem_master_port = piobus.slave 107 cpu_seq.pio_slave_port = piobus.master |
108 109 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 110 # 111 # Add controllers and sequencers to the appropriate lists 112 # 113 cpu_sequencers.append(cpu_seq) 114 l1_cntrl_nodes.append(l1_cntrl) 115 --- 78 unchanged lines hidden --- |