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> l1_cntrl = L1Cache_Controller(version = i,
> cntrl_id = cntrl_count,
> L1IcacheMemory = l1i_cache,
> L1DcacheMemory = l1d_cache,
> l2_select_num_bits = l2_bits)
>
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> l1_cntrl.sequencer = cpu_seq
>
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< l1_cntrl = L1Cache_Controller(version = i,
< cntrl_id = cntrl_count,
< sequencer = cpu_seq,
< L1IcacheMemory = l1i_cache,
< L1DcacheMemory = l1d_cache,
< l2_select_num_bits = l2_bits)
<