1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
51def create_system(options, system, piobus, dma_ports, ruby_system):
52
53 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
54 panic("This script requires the MOESI_CMP_directory protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 l2_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72 l2_bits = int(math.log(options.num_l2caches, 2))
73 block_size_bits = int(math.log(options.cacheline_size, 2))
74
75 cntrl_count = 0
76
77 for i in xrange(options.num_cpus):
78 #
79 # First create the Ruby objects associated with this cpu
80 #
81 l1i_cache = L1Cache(size = options.l1i_size,
82 assoc = options.l1i_assoc,
83 start_index_bit = block_size_bits,
84 is_icache = True)
85 l1d_cache = L1Cache(size = options.l1d_size,
86 assoc = options.l1d_assoc,
87 start_index_bit = block_size_bits,
88 is_icache = False)
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 cntrl_id = cntrl_count,
92 L1Icache = l1i_cache,
93 L1Dcache = l1d_cache,
94 l2_select_num_bits = l2_bits,
95 send_evictions = (
96 options.cpu_type == "detailed"),
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
51def create_system(options, system, piobus, dma_ports, ruby_system):
52
53 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
54 panic("This script requires the MOESI_CMP_directory protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 l2_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72 l2_bits = int(math.log(options.num_l2caches, 2))
73 block_size_bits = int(math.log(options.cacheline_size, 2))
74
75 cntrl_count = 0
76
77 for i in xrange(options.num_cpus):
78 #
79 # First create the Ruby objects associated with this cpu
80 #
81 l1i_cache = L1Cache(size = options.l1i_size,
82 assoc = options.l1i_assoc,
83 start_index_bit = block_size_bits,
84 is_icache = True)
85 l1d_cache = L1Cache(size = options.l1d_size,
86 assoc = options.l1d_assoc,
87 start_index_bit = block_size_bits,
88 is_icache = False)
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 cntrl_id = cntrl_count,
92 L1Icache = l1i_cache,
93 L1Dcache = l1d_cache,
94 l2_select_num_bits = l2_bits,
95 send_evictions = (
96 options.cpu_type == "detailed"),
|
| 97 transitions_per_cycle = options.ports,
|
97 ruby_system = ruby_system)
98
99 cpu_seq = RubySequencer(version = i,
100 icache = l1i_cache,
101 dcache = l1d_cache,
102 ruby_system = ruby_system)
103
104 l1_cntrl.sequencer = cpu_seq
105
106 if piobus != None:
107 cpu_seq.pio_port = piobus.slave
108
109 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
110 #
111 # Add controllers and sequencers to the appropriate lists
112 #
113 cpu_sequencers.append(cpu_seq)
114 l1_cntrl_nodes.append(l1_cntrl)
115
116 cntrl_count += 1
117
118 l2_index_start = block_size_bits + l2_bits
119
120 for i in xrange(options.num_l2caches):
121 #
122 # First create the Ruby objects associated with this cpu
123 #
124 l2_cache = L2Cache(size = options.l2_size,
125 assoc = options.l2_assoc,
126 start_index_bit = l2_index_start)
127
128 l2_cntrl = L2Cache_Controller(version = i,
129 cntrl_id = cntrl_count,
130 L2cache = l2_cache,
| 98 ruby_system = ruby_system)
99
100 cpu_seq = RubySequencer(version = i,
101 icache = l1i_cache,
102 dcache = l1d_cache,
103 ruby_system = ruby_system)
104
105 l1_cntrl.sequencer = cpu_seq
106
107 if piobus != None:
108 cpu_seq.pio_port = piobus.slave
109
110 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
111 #
112 # Add controllers and sequencers to the appropriate lists
113 #
114 cpu_sequencers.append(cpu_seq)
115 l1_cntrl_nodes.append(l1_cntrl)
116
117 cntrl_count += 1
118
119 l2_index_start = block_size_bits + l2_bits
120
121 for i in xrange(options.num_l2caches):
122 #
123 # First create the Ruby objects associated with this cpu
124 #
125 l2_cache = L2Cache(size = options.l2_size,
126 assoc = options.l2_assoc,
127 start_index_bit = l2_index_start)
128
129 l2_cntrl = L2Cache_Controller(version = i,
130 cntrl_id = cntrl_count,
131 L2cache = l2_cache,
|
| 132 transitions_per_cycle = options.ports,
|
131 ruby_system = ruby_system)
132
133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 cntrl_count += 1
137
138 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
139 assert(phys_mem_size % options.num_dirs == 0)
140 mem_module_size = phys_mem_size / options.num_dirs
141
142 # Run each of the ruby memory controllers at a ratio of the frequency of
143 # the ruby system.
144 # clk_divider value is a fix to pass regression.
145 ruby_system.memctrl_clk_domain = DerivedClockDomain(
146 clk_domain=ruby_system.clk_domain,
147 clk_divider=3)
148
149 for i in xrange(options.num_dirs):
150 #
151 # Create the Ruby objects associated with the directory controller
152 #
153
154 mem_cntrl = RubyMemoryControl(
155 clk_domain = ruby_system.memctrl_clk_domain,
156 version = i,
157 ruby_system = ruby_system)
158
159 dir_size = MemorySize('0B')
160 dir_size.value = mem_module_size
161
162 dir_cntrl = Directory_Controller(version = i,
163 cntrl_id = cntrl_count,
164 directory = \
165 RubyDirectoryMemory(version = i,
166 size = dir_size,
167 use_map = options.use_map),
168 memBuffer = mem_cntrl,
| 133 ruby_system = ruby_system)
134
135 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
136 l2_cntrl_nodes.append(l2_cntrl)
137
138 cntrl_count += 1
139
140 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
141 assert(phys_mem_size % options.num_dirs == 0)
142 mem_module_size = phys_mem_size / options.num_dirs
143
144 # Run each of the ruby memory controllers at a ratio of the frequency of
145 # the ruby system.
146 # clk_divider value is a fix to pass regression.
147 ruby_system.memctrl_clk_domain = DerivedClockDomain(
148 clk_domain=ruby_system.clk_domain,
149 clk_divider=3)
150
151 for i in xrange(options.num_dirs):
152 #
153 # Create the Ruby objects associated with the directory controller
154 #
155
156 mem_cntrl = RubyMemoryControl(
157 clk_domain = ruby_system.memctrl_clk_domain,
158 version = i,
159 ruby_system = ruby_system)
160
161 dir_size = MemorySize('0B')
162 dir_size.value = mem_module_size
163
164 dir_cntrl = Directory_Controller(version = i,
165 cntrl_id = cntrl_count,
166 directory = \
167 RubyDirectoryMemory(version = i,
168 size = dir_size,
169 use_map = options.use_map),
170 memBuffer = mem_cntrl,
|
| 171 transitions_per_cycle = options.ports,
|
169 ruby_system = ruby_system)
170
171 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
172 dir_cntrl_nodes.append(dir_cntrl)
173
174 cntrl_count += 1
175
176 for i, dma_port in enumerate(dma_ports):
177 #
178 # Create the Ruby objects associated with the dma controller
179 #
180 dma_seq = DMASequencer(version = i,
181 ruby_system = ruby_system)
182
183 dma_cntrl = DMA_Controller(version = i,
184 cntrl_id = cntrl_count,
185 dma_sequencer = dma_seq,
| 172 ruby_system = ruby_system)
173
174 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
175 dir_cntrl_nodes.append(dir_cntrl)
176
177 cntrl_count += 1
178
179 for i, dma_port in enumerate(dma_ports):
180 #
181 # Create the Ruby objects associated with the dma controller
182 #
183 dma_seq = DMASequencer(version = i,
184 ruby_system = ruby_system)
185
186 dma_cntrl = DMA_Controller(version = i,
187 cntrl_id = cntrl_count,
188 dma_sequencer = dma_seq,
|
| 189 transitions_per_cycle = options.ports,
|
186 ruby_system = ruby_system)
187
188 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
189 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
190 dma_cntrl_nodes.append(dma_cntrl)
191 cntrl_count += 1
192
193 all_cntrls = l1_cntrl_nodes + \
194 l2_cntrl_nodes + \
195 dir_cntrl_nodes + \
196 dma_cntrl_nodes
197
198 topology = create_topology(all_cntrls, options)
199
200 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 190 ruby_system = ruby_system)
191
192 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
193 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
194 dma_cntrl_nodes.append(dma_cntrl)
195 cntrl_count += 1
196
197 all_cntrls = l1_cntrl_nodes + \
198 l2_cntrl_nodes + \
199 dir_cntrl_nodes + \
200 dma_cntrl_nodes
201
202 topology = create_topology(all_cntrls, options)
203
204 return (cpu_sequencers, dir_cntrl_nodes, topology)
|