1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
51def create_system(options, system, piobus, dma_ports, ruby_system):
52
53 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
54 panic("This script requires the MOESI_CMP_directory protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 l2_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72 l2_bits = int(math.log(options.num_l2caches, 2))
73 block_size_bits = int(math.log(options.cacheline_size, 2))
74
75 cntrl_count = 0
76
77 for i in xrange(options.num_cpus):
78 #
79 # First create the Ruby objects associated with this cpu
80 #
81 l1i_cache = L1Cache(size = options.l1i_size,
82 assoc = options.l1i_assoc,
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
51def create_system(options, system, piobus, dma_ports, ruby_system):
52
53 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
54 panic("This script requires the MOESI_CMP_directory protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 l2_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72 l2_bits = int(math.log(options.num_l2caches, 2))
73 block_size_bits = int(math.log(options.cacheline_size, 2))
74
75 cntrl_count = 0
76
77 for i in xrange(options.num_cpus):
78 #
79 # First create the Ruby objects associated with this cpu
80 #
81 l1i_cache = L1Cache(size = options.l1i_size,
82 assoc = options.l1i_assoc,
|
83 start_index_bit = block_size_bits)
| 83 start_index_bit = block_size_bits,
84 is_icache = True)
|
84 l1d_cache = L1Cache(size = options.l1d_size,
85 assoc = options.l1d_assoc,
| 85 l1d_cache = L1Cache(size = options.l1d_size,
86 assoc = options.l1d_assoc,
|
86 start_index_bit = block_size_bits)
| 87 start_index_bit = block_size_bits,
88 is_icache = False)
|
87
88 l1_cntrl = L1Cache_Controller(version = i,
89 cntrl_id = cntrl_count,
90 L1IcacheMemory = l1i_cache,
91 L1DcacheMemory = l1d_cache,
92 l2_select_num_bits = l2_bits,
93 send_evictions = (
94 options.cpu_type == "detailed"),
95 ruby_system = ruby_system)
96
97 cpu_seq = RubySequencer(version = i,
98 icache = l1i_cache,
99 dcache = l1d_cache,
100 ruby_system = ruby_system)
101
102 l1_cntrl.sequencer = cpu_seq
103
104 if piobus != None:
105 cpu_seq.pio_port = piobus.slave
106
107 exec("system.l1_cntrl%d = l1_cntrl" % i)
108 #
109 # Add controllers and sequencers to the appropriate lists
110 #
111 cpu_sequencers.append(cpu_seq)
112 l1_cntrl_nodes.append(l1_cntrl)
113
114 cntrl_count += 1
115
116 l2_index_start = block_size_bits + l2_bits
117
118 for i in xrange(options.num_l2caches):
119 #
120 # First create the Ruby objects associated with this cpu
121 #
122 l2_cache = L2Cache(size = options.l2_size,
123 assoc = options.l2_assoc,
124 start_index_bit = l2_index_start)
125
126 l2_cntrl = L2Cache_Controller(version = i,
127 cntrl_id = cntrl_count,
128 L2cacheMemory = l2_cache,
129 ruby_system = ruby_system)
130
131 exec("system.l2_cntrl%d = l2_cntrl" % i)
132 l2_cntrl_nodes.append(l2_cntrl)
133
134 cntrl_count += 1
135
136 phys_mem_size = sum(map(lambda mem: mem.range.size(),
137 system.memories.unproxy(system)))
138 mem_module_size = phys_mem_size / options.num_dirs
139
140 for i in xrange(options.num_dirs):
141 #
142 # Create the Ruby objects associated with the directory controller
143 #
144
145 mem_cntrl = RubyMemoryControl(version = i,
146 ruby_system = ruby_system)
147
148 dir_size = MemorySize('0B')
149 dir_size.value = mem_module_size
150
151 dir_cntrl = Directory_Controller(version = i,
152 cntrl_id = cntrl_count,
153 directory = \
154 RubyDirectoryMemory(version = i,
155 size = dir_size),
156 memBuffer = mem_cntrl,
157 ruby_system = ruby_system)
158
159 exec("system.dir_cntrl%d = dir_cntrl" % i)
160 dir_cntrl_nodes.append(dir_cntrl)
161
162 cntrl_count += 1
163
164 for i, dma_port in enumerate(dma_ports):
165 #
166 # Create the Ruby objects associated with the dma controller
167 #
168 dma_seq = DMASequencer(version = i,
169 ruby_system = ruby_system)
170
171 dma_cntrl = DMA_Controller(version = i,
172 cntrl_id = cntrl_count,
173 dma_sequencer = dma_seq,
174 ruby_system = ruby_system)
175
176 exec("system.dma_cntrl%d = dma_cntrl" % i)
177 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
178 dma_cntrl_nodes.append(dma_cntrl)
179 cntrl_count += 1
180
181 all_cntrls = l1_cntrl_nodes + \
182 l2_cntrl_nodes + \
183 dir_cntrl_nodes + \
184 dma_cntrl_nodes
185
186 topology = create_topology(all_cntrls, options)
187
188 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 89
90 l1_cntrl = L1Cache_Controller(version = i,
91 cntrl_id = cntrl_count,
92 L1IcacheMemory = l1i_cache,
93 L1DcacheMemory = l1d_cache,
94 l2_select_num_bits = l2_bits,
95 send_evictions = (
96 options.cpu_type == "detailed"),
97 ruby_system = ruby_system)
98
99 cpu_seq = RubySequencer(version = i,
100 icache = l1i_cache,
101 dcache = l1d_cache,
102 ruby_system = ruby_system)
103
104 l1_cntrl.sequencer = cpu_seq
105
106 if piobus != None:
107 cpu_seq.pio_port = piobus.slave
108
109 exec("system.l1_cntrl%d = l1_cntrl" % i)
110 #
111 # Add controllers and sequencers to the appropriate lists
112 #
113 cpu_sequencers.append(cpu_seq)
114 l1_cntrl_nodes.append(l1_cntrl)
115
116 cntrl_count += 1
117
118 l2_index_start = block_size_bits + l2_bits
119
120 for i in xrange(options.num_l2caches):
121 #
122 # First create the Ruby objects associated with this cpu
123 #
124 l2_cache = L2Cache(size = options.l2_size,
125 assoc = options.l2_assoc,
126 start_index_bit = l2_index_start)
127
128 l2_cntrl = L2Cache_Controller(version = i,
129 cntrl_id = cntrl_count,
130 L2cacheMemory = l2_cache,
131 ruby_system = ruby_system)
132
133 exec("system.l2_cntrl%d = l2_cntrl" % i)
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 cntrl_count += 1
137
138 phys_mem_size = sum(map(lambda mem: mem.range.size(),
139 system.memories.unproxy(system)))
140 mem_module_size = phys_mem_size / options.num_dirs
141
142 for i in xrange(options.num_dirs):
143 #
144 # Create the Ruby objects associated with the directory controller
145 #
146
147 mem_cntrl = RubyMemoryControl(version = i,
148 ruby_system = ruby_system)
149
150 dir_size = MemorySize('0B')
151 dir_size.value = mem_module_size
152
153 dir_cntrl = Directory_Controller(version = i,
154 cntrl_id = cntrl_count,
155 directory = \
156 RubyDirectoryMemory(version = i,
157 size = dir_size),
158 memBuffer = mem_cntrl,
159 ruby_system = ruby_system)
160
161 exec("system.dir_cntrl%d = dir_cntrl" % i)
162 dir_cntrl_nodes.append(dir_cntrl)
163
164 cntrl_count += 1
165
166 for i, dma_port in enumerate(dma_ports):
167 #
168 # Create the Ruby objects associated with the dma controller
169 #
170 dma_seq = DMASequencer(version = i,
171 ruby_system = ruby_system)
172
173 dma_cntrl = DMA_Controller(version = i,
174 cntrl_id = cntrl_count,
175 dma_sequencer = dma_seq,
176 ruby_system = ruby_system)
177
178 exec("system.dma_cntrl%d = dma_cntrl" % i)
179 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
180 dma_cntrl_nodes.append(dma_cntrl)
181 cntrl_count += 1
182
183 all_cntrls = l1_cntrl_nodes + \
184 l2_cntrl_nodes + \
185 dir_cntrl_nodes + \
186 dma_cntrl_nodes
187
188 topology = create_topology(all_cntrls, options)
189
190 return (cpu_sequencers, dir_cntrl_nodes, topology)
|