1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
|
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39 latency = 3
40
41#
42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45 latency = 15
46
47def define_options(parser):
48 return
49
50def create_system(options, system, piobus, dma_ports, ruby_system):
51
52 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
53 panic("This script requires the MOESI_CMP_directory protocol to be built.")
54
55 cpu_sequencers = []
56
57 #
58 # The ruby network creation expects the list of nodes in the system to be
59 # consistent with the NetDest list. Therefore the l1 controller nodes must be
60 # listed before the directory nodes and directory nodes before dma nodes, etc.
61 #
62 l1_cntrl_nodes = []
63 l2_cntrl_nodes = []
64 dir_cntrl_nodes = []
65 dma_cntrl_nodes = []
66
67 #
68 # Must create the individual controllers before the network to ensure the
69 # controller constructors are called before the network constructor
70 #
71 l2_bits = int(math.log(options.num_l2caches, 2))
72 block_size_bits = int(math.log(options.cacheline_size, 2))
73
74 cntrl_count = 0
75
76 for i in xrange(options.num_cpus):
77 #
78 # First create the Ruby objects associated with this cpu
79 #
80 l1i_cache = L1Cache(size = options.l1i_size,
81 assoc = options.l1i_assoc,
82 start_index_bit = block_size_bits)
83 l1d_cache = L1Cache(size = options.l1d_size,
84 assoc = options.l1d_assoc,
85 start_index_bit = block_size_bits)
86
87 l1_cntrl = L1Cache_Controller(version = i,
88 cntrl_id = cntrl_count,
89 L1IcacheMemory = l1i_cache,
90 L1DcacheMemory = l1d_cache,
91 l2_select_num_bits = l2_bits,
92 send_evictions = (
93 options.cpu_type == "detailed"),
94 ruby_system = ruby_system)
95
96 cpu_seq = RubySequencer(version = i,
97 icache = l1i_cache,
98 dcache = l1d_cache,
99 ruby_system = ruby_system)
100
101 l1_cntrl.sequencer = cpu_seq
102
103 if piobus != None:
104 cpu_seq.pio_port = piobus.slave
105
106 exec("system.l1_cntrl%d = l1_cntrl" % i)
107 #
108 # Add controllers and sequencers to the appropriate lists
109 #
110 cpu_sequencers.append(cpu_seq)
111 l1_cntrl_nodes.append(l1_cntrl)
112
113 cntrl_count += 1
114
115 l2_index_start = block_size_bits + l2_bits
116
117 for i in xrange(options.num_l2caches):
118 #
119 # First create the Ruby objects associated with this cpu
120 #
121 l2_cache = L2Cache(size = options.l2_size,
122 assoc = options.l2_assoc,
123 start_index_bit = l2_index_start)
124
125 l2_cntrl = L2Cache_Controller(version = i,
126 cntrl_id = cntrl_count,
127 L2cacheMemory = l2_cache,
128 ruby_system = ruby_system)
129
130 exec("system.l2_cntrl%d = l2_cntrl" % i)
131 l2_cntrl_nodes.append(l2_cntrl)
132
133 cntrl_count += 1
134
135 phys_mem_size = 0
136 for mem in system.memories.unproxy(system):
137 phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
138 mem_module_size = phys_mem_size / options.num_dirs
139
140 for i in xrange(options.num_dirs):
141 #
142 # Create the Ruby objects associated with the directory controller
143 #
144
145 mem_cntrl = RubyMemoryControl(version = i)
146
147 dir_size = MemorySize('0B')
148 dir_size.value = mem_module_size
149
150 dir_cntrl = Directory_Controller(version = i,
151 cntrl_id = cntrl_count,
152 directory = \
153 RubyDirectoryMemory(version = i,
154 size = dir_size),
155 memBuffer = mem_cntrl,
156 ruby_system = ruby_system)
157
158 exec("system.dir_cntrl%d = dir_cntrl" % i)
159 dir_cntrl_nodes.append(dir_cntrl)
160
161 cntrl_count += 1
162
163 for i, dma_port in enumerate(dma_ports):
164 #
165 # Create the Ruby objects associated with the dma controller
166 #
167 dma_seq = DMASequencer(version = i,
168 ruby_system = ruby_system)
169
170 dma_cntrl = DMA_Controller(version = i,
171 cntrl_id = cntrl_count,
172 dma_sequencer = dma_seq,
173 ruby_system = ruby_system)
174
175 exec("system.dma_cntrl%d = dma_cntrl" % i)
176 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
177 dma_cntrl_nodes.append(dma_cntrl)
178 cntrl_count += 1
179
180 all_cntrls = l1_cntrl_nodes + \
181 l2_cntrl_nodes + \
182 dir_cntrl_nodes + \
183 dma_cntrl_nodes
184
| 35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
51def create_system(options, system, piobus, dma_ports, ruby_system):
52
53 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
54 panic("This script requires the MOESI_CMP_directory protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 l2_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72 l2_bits = int(math.log(options.num_l2caches, 2))
73 block_size_bits = int(math.log(options.cacheline_size, 2))
74
75 cntrl_count = 0
76
77 for i in xrange(options.num_cpus):
78 #
79 # First create the Ruby objects associated with this cpu
80 #
81 l1i_cache = L1Cache(size = options.l1i_size,
82 assoc = options.l1i_assoc,
83 start_index_bit = block_size_bits)
84 l1d_cache = L1Cache(size = options.l1d_size,
85 assoc = options.l1d_assoc,
86 start_index_bit = block_size_bits)
87
88 l1_cntrl = L1Cache_Controller(version = i,
89 cntrl_id = cntrl_count,
90 L1IcacheMemory = l1i_cache,
91 L1DcacheMemory = l1d_cache,
92 l2_select_num_bits = l2_bits,
93 send_evictions = (
94 options.cpu_type == "detailed"),
95 ruby_system = ruby_system)
96
97 cpu_seq = RubySequencer(version = i,
98 icache = l1i_cache,
99 dcache = l1d_cache,
100 ruby_system = ruby_system)
101
102 l1_cntrl.sequencer = cpu_seq
103
104 if piobus != None:
105 cpu_seq.pio_port = piobus.slave
106
107 exec("system.l1_cntrl%d = l1_cntrl" % i)
108 #
109 # Add controllers and sequencers to the appropriate lists
110 #
111 cpu_sequencers.append(cpu_seq)
112 l1_cntrl_nodes.append(l1_cntrl)
113
114 cntrl_count += 1
115
116 l2_index_start = block_size_bits + l2_bits
117
118 for i in xrange(options.num_l2caches):
119 #
120 # First create the Ruby objects associated with this cpu
121 #
122 l2_cache = L2Cache(size = options.l2_size,
123 assoc = options.l2_assoc,
124 start_index_bit = l2_index_start)
125
126 l2_cntrl = L2Cache_Controller(version = i,
127 cntrl_id = cntrl_count,
128 L2cacheMemory = l2_cache,
129 ruby_system = ruby_system)
130
131 exec("system.l2_cntrl%d = l2_cntrl" % i)
132 l2_cntrl_nodes.append(l2_cntrl)
133
134 cntrl_count += 1
135
136 phys_mem_size = 0
137 for mem in system.memories.unproxy(system):
138 phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
139 mem_module_size = phys_mem_size / options.num_dirs
140
141 for i in xrange(options.num_dirs):
142 #
143 # Create the Ruby objects associated with the directory controller
144 #
145
146 mem_cntrl = RubyMemoryControl(version = i)
147
148 dir_size = MemorySize('0B')
149 dir_size.value = mem_module_size
150
151 dir_cntrl = Directory_Controller(version = i,
152 cntrl_id = cntrl_count,
153 directory = \
154 RubyDirectoryMemory(version = i,
155 size = dir_size),
156 memBuffer = mem_cntrl,
157 ruby_system = ruby_system)
158
159 exec("system.dir_cntrl%d = dir_cntrl" % i)
160 dir_cntrl_nodes.append(dir_cntrl)
161
162 cntrl_count += 1
163
164 for i, dma_port in enumerate(dma_ports):
165 #
166 # Create the Ruby objects associated with the dma controller
167 #
168 dma_seq = DMASequencer(version = i,
169 ruby_system = ruby_system)
170
171 dma_cntrl = DMA_Controller(version = i,
172 cntrl_id = cntrl_count,
173 dma_sequencer = dma_seq,
174 ruby_system = ruby_system)
175
176 exec("system.dma_cntrl%d = dma_cntrl" % i)
177 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
178 dma_cntrl_nodes.append(dma_cntrl)
179 cntrl_count += 1
180
181 all_cntrls = l1_cntrl_nodes + \
182 l2_cntrl_nodes + \
183 dir_cntrl_nodes + \
184 dma_cntrl_nodes
185
|