1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39 latency = 3
40
41#
42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45 latency = 15
46
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39 latency = 3
40
41#
42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45 latency = 15
46
|
47def create_system(options, phys_mem, piobus, dma_devices):
48
49 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
50 panic("This script requires the MOESI_CMP_directory protocol to be built.")
51
52 cpu_sequencers = []
53
54 #
55 # The ruby network creation expects the list of nodes in the system to be
56 # consistent with the NetDest list. Therefore the l1 controller nodes must be
57 # listed before the directory nodes and directory nodes before dma nodes, etc.
58 #
59 l1_cntrl_nodes = []
60 l2_cntrl_nodes = []
61 dir_cntrl_nodes = []
62 dma_cntrl_nodes = []
63
64 #
65 # Must create the individual controllers before the network to ensure the
66 # controller constructors are called before the network constructor
67 #
68
69 for i in xrange(options.num_cpus):
70 #
71 # First create the Ruby objects associated with this cpu
72 #
73 l1i_cache = L1Cache(size = options.l1i_size,
74 assoc = options.l1i_assoc)
75 l1d_cache = L1Cache(size = options.l1d_size,
76 assoc = options.l1d_assoc)
77
78 cpu_seq = RubySequencer(version = i,
79 icache = l1i_cache,
80 dcache = l1d_cache,
81 physMemPort = phys_mem.port,
82 physmem = phys_mem)
83
84 if piobus != None:
85 cpu_seq.pio_port = piobus.port
86
87 l1_cntrl = L1Cache_Controller(version = i,
88 sequencer = cpu_seq,
89 L1IcacheMemory = l1i_cache,
90 L1DcacheMemory = l1d_cache,
91 l2_select_num_bits = \
92 math.log(options.num_l2caches, 2))
93 #
94 # Add controllers and sequencers to the appropriate lists
95 #
96 cpu_sequencers.append(cpu_seq)
97 l1_cntrl_nodes.append(l1_cntrl)
98
99 for i in xrange(options.num_l2caches):
100 #
101 # First create the Ruby objects associated with this cpu
102 #
103 l2_cache = L2Cache(size = options.l2_size,
104 assoc = options.l2_assoc)
105
106 l2_cntrl = L2Cache_Controller(version = i,
107 L2cacheMemory = l2_cache)
108
109 l2_cntrl_nodes.append(l2_cntrl)
110
111 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
112 mem_module_size = phys_mem_size / options.num_dirs
113
114 for i in xrange(options.num_dirs):
115 #
116 # Create the Ruby objects associated with the directory controller
117 #
118
119 mem_cntrl = RubyMemoryControl(version = i)
120
121 dir_size = MemorySize('0B')
122 dir_size.value = mem_module_size
123
124 dir_cntrl = Directory_Controller(version = i,
125 directory = \
126 RubyDirectoryMemory(version = i,
127 size = dir_size),
128 memBuffer = mem_cntrl)
129
130 dir_cntrl_nodes.append(dir_cntrl)
131
132 for i, dma_device in enumerate(dma_devices):
133 #
134 # Create the Ruby objects associated with the dma controller
135 #
136 dma_seq = DMASequencer(version = i,
137 physMemPort = phys_mem.port,
138 physmem = phys_mem)
139
140 dma_cntrl = DMA_Controller(version = i,
141 dma_sequencer = dma_seq)
142
143 dma_cntrl.dma_sequencer.port = dma_device.dma
144 dma_cntrl_nodes.append(dma_cntrl)
145
146 all_cntrls = l1_cntrl_nodes + \
147 l2_cntrl_nodes + \
148 dir_cntrl_nodes + \
149 dma_cntrl_nodes
150
151 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
| 50def create_system(options, phys_mem, piobus, dma_devices):
51
52 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
53 panic("This script requires the MOESI_CMP_directory protocol to be built.")
54
55 cpu_sequencers = []
56
57 #
58 # The ruby network creation expects the list of nodes in the system to be
59 # consistent with the NetDest list. Therefore the l1 controller nodes must be
60 # listed before the directory nodes and directory nodes before dma nodes, etc.
61 #
62 l1_cntrl_nodes = []
63 l2_cntrl_nodes = []
64 dir_cntrl_nodes = []
65 dma_cntrl_nodes = []
66
67 #
68 # Must create the individual controllers before the network to ensure the
69 # controller constructors are called before the network constructor
70 #
71
72 for i in xrange(options.num_cpus):
73 #
74 # First create the Ruby objects associated with this cpu
75 #
76 l1i_cache = L1Cache(size = options.l1i_size,
77 assoc = options.l1i_assoc)
78 l1d_cache = L1Cache(size = options.l1d_size,
79 assoc = options.l1d_assoc)
80
81 cpu_seq = RubySequencer(version = i,
82 icache = l1i_cache,
83 dcache = l1d_cache,
84 physMemPort = phys_mem.port,
85 physmem = phys_mem)
86
87 if piobus != None:
88 cpu_seq.pio_port = piobus.port
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 sequencer = cpu_seq,
92 L1IcacheMemory = l1i_cache,
93 L1DcacheMemory = l1d_cache,
94 l2_select_num_bits = \
95 math.log(options.num_l2caches, 2))
96 #
97 # Add controllers and sequencers to the appropriate lists
98 #
99 cpu_sequencers.append(cpu_seq)
100 l1_cntrl_nodes.append(l1_cntrl)
101
102 for i in xrange(options.num_l2caches):
103 #
104 # First create the Ruby objects associated with this cpu
105 #
106 l2_cache = L2Cache(size = options.l2_size,
107 assoc = options.l2_assoc)
108
109 l2_cntrl = L2Cache_Controller(version = i,
110 L2cacheMemory = l2_cache)
111
112 l2_cntrl_nodes.append(l2_cntrl)
113
114 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
115 mem_module_size = phys_mem_size / options.num_dirs
116
117 for i in xrange(options.num_dirs):
118 #
119 # Create the Ruby objects associated with the directory controller
120 #
121
122 mem_cntrl = RubyMemoryControl(version = i)
123
124 dir_size = MemorySize('0B')
125 dir_size.value = mem_module_size
126
127 dir_cntrl = Directory_Controller(version = i,
128 directory = \
129 RubyDirectoryMemory(version = i,
130 size = dir_size),
131 memBuffer = mem_cntrl)
132
133 dir_cntrl_nodes.append(dir_cntrl)
134
135 for i, dma_device in enumerate(dma_devices):
136 #
137 # Create the Ruby objects associated with the dma controller
138 #
139 dma_seq = DMASequencer(version = i,
140 physMemPort = phys_mem.port,
141 physmem = phys_mem)
142
143 dma_cntrl = DMA_Controller(version = i,
144 dma_sequencer = dma_seq)
145
146 dma_cntrl.dma_sequencer.port = dma_device.dma
147 dma_cntrl_nodes.append(dma_cntrl)
148
149 all_cntrls = l1_cntrl_nodes + \
150 l2_cntrl_nodes + \
151 dir_cntrl_nodes + \
152 dma_cntrl_nodes
153
154 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|