1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from m5.util import addToPath
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def create_system(options, phys_mem, piobus, dma_devices):
49
50 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
51 panic("This script requires the MOESI_CMP_directory protocol to be built.")
52
53 cpu_sequencers = []
54
55 #
56 # The ruby network creation expects the list of nodes in the system to be
57 # consistent with the NetDest list. Therefore the l1 controller nodes must be
58 # listed before the directory nodes and directory nodes before dma nodes, etc.
59 #
60 l1_cntrl_nodes = []
61 l2_cntrl_nodes = []
62 dir_cntrl_nodes = []
63 dma_cntrl_nodes = []
64
65 #
66 # Must create the individual controllers before the network to ensure the
67 # controller constructors are called before the network constructor
68 #
69
70 for i in xrange(options.num_cpus):
71 #
72 # First create the Ruby objects associated with this cpu
73 #
74 l1i_cache = L1Cache(size = options.l1i_size,
75 assoc = options.l1i_assoc)
76 l1d_cache = L1Cache(size = options.l1d_size,
77 assoc = options.l1d_assoc)
78
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from m5.util import addToPath
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def create_system(options, phys_mem, piobus, dma_devices):
49
50 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
51 panic("This script requires the MOESI_CMP_directory protocol to be built.")
52
53 cpu_sequencers = []
54
55 #
56 # The ruby network creation expects the list of nodes in the system to be
57 # consistent with the NetDest list. Therefore the l1 controller nodes must be
58 # listed before the directory nodes and directory nodes before dma nodes, etc.
59 #
60 l1_cntrl_nodes = []
61 l2_cntrl_nodes = []
62 dir_cntrl_nodes = []
63 dma_cntrl_nodes = []
64
65 #
66 # Must create the individual controllers before the network to ensure the
67 # controller constructors are called before the network constructor
68 #
69
70 for i in xrange(options.num_cpus):
71 #
72 # First create the Ruby objects associated with this cpu
73 #
74 l1i_cache = L1Cache(size = options.l1i_size,
75 assoc = options.l1i_assoc)
76 l1d_cache = L1Cache(size = options.l1d_size,
77 assoc = options.l1d_assoc)
78
|
80 dcache = l1d_cache,
81 physMemPort = phys_mem.port,
82 physmem = phys_mem)
83
84 if piobus != None:
85 cpu_seq.pio_port = piobus.port
86
87 l1_cntrl = L1Cache_Controller(version = i,
88 sequencer = cpu_seq,
89 L1IcacheMemory = l1i_cache,
90 L1DcacheMemory = l1d_cache,
91 l2_select_num_bits = \
92 math.log(options.num_l2caches, 2))
93 #
94 # Add controllers and sequencers to the appropriate lists
95 #
96 cpu_sequencers.append(cpu_seq)
97 l1_cntrl_nodes.append(l1_cntrl)
98
99 for i in xrange(options.num_l2caches):
100 #
101 # First create the Ruby objects associated with this cpu
102 #
103 l2_cache = L2Cache(size = options.l2_size,
104 assoc = options.l2_assoc)
105
106 l2_cntrl = L2Cache_Controller(version = i,
107 L2cacheMemory = l2_cache)
108
109 l2_cntrl_nodes.append(l2_cntrl)
110
111 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
112 mem_module_size = phys_mem_size / options.num_dirs
113
114 for i in xrange(options.num_dirs):
115 #
116 # Create the Ruby objects associated with the directory controller
117 #
118
119 mem_cntrl = RubyMemoryControl(version = i)
120
121 dir_size = MemorySize('0B')
122 dir_size.value = mem_module_size
123
124 dir_cntrl = Directory_Controller(version = i,
125 directory = \
126 RubyDirectoryMemory(version = i,
127 size = dir_size),
128 memBuffer = mem_cntrl)
129
130 dir_cntrl_nodes.append(dir_cntrl)
131
132 for i, dma_device in enumerate(dma_devices):
133 #
134 # Create the Ruby objects associated with the dma controller
135 #
136 dma_seq = DMASequencer(version = i,
137 physMemPort = phys_mem.port,
138 physmem = phys_mem)
139
140 dma_cntrl = DMA_Controller(version = i,
141 dma_sequencer = dma_seq)
142
143 dma_cntrl.dma_sequencer.port = dma_device.dma
144 dma_cntrl_nodes.append(dma_cntrl)
145
146 all_cntrls = l1_cntrl_nodes + \
147 l2_cntrl_nodes + \
148 dir_cntrl_nodes + \
149 dma_cntrl_nodes
150
151 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
| 81 dcache = l1d_cache,
82 physMemPort = phys_mem.port,
83 physmem = phys_mem)
84
85 if piobus != None:
86 cpu_seq.pio_port = piobus.port
87
88 l1_cntrl = L1Cache_Controller(version = i,
89 sequencer = cpu_seq,
90 L1IcacheMemory = l1i_cache,
91 L1DcacheMemory = l1d_cache,
92 l2_select_num_bits = \
93 math.log(options.num_l2caches, 2))
94 #
95 # Add controllers and sequencers to the appropriate lists
96 #
97 cpu_sequencers.append(cpu_seq)
98 l1_cntrl_nodes.append(l1_cntrl)
99
100 for i in xrange(options.num_l2caches):
101 #
102 # First create the Ruby objects associated with this cpu
103 #
104 l2_cache = L2Cache(size = options.l2_size,
105 assoc = options.l2_assoc)
106
107 l2_cntrl = L2Cache_Controller(version = i,
108 L2cacheMemory = l2_cache)
109
110 l2_cntrl_nodes.append(l2_cntrl)
111
112 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
113 mem_module_size = phys_mem_size / options.num_dirs
114
115 for i in xrange(options.num_dirs):
116 #
117 # Create the Ruby objects associated with the directory controller
118 #
119
120 mem_cntrl = RubyMemoryControl(version = i)
121
122 dir_size = MemorySize('0B')
123 dir_size.value = mem_module_size
124
125 dir_cntrl = Directory_Controller(version = i,
126 directory = \
127 RubyDirectoryMemory(version = i,
128 size = dir_size),
129 memBuffer = mem_cntrl)
130
131 dir_cntrl_nodes.append(dir_cntrl)
132
133 for i, dma_device in enumerate(dma_devices):
134 #
135 # Create the Ruby objects associated with the dma controller
136 #
137 dma_seq = DMASequencer(version = i,
138 physMemPort = phys_mem.port,
139 physmem = phys_mem)
140
141 dma_cntrl = DMA_Controller(version = i,
142 dma_sequencer = dma_seq)
143
144 dma_cntrl.dma_sequencer.port = dma_device.dma
145 dma_cntrl_nodes.append(dma_cntrl)
146
147 all_cntrls = l1_cntrl_nodes + \
148 l2_cntrl_nodes + \
149 dir_cntrl_nodes + \
150 dma_cntrl_nodes
151
152 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|