1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
51def create_system(options, full_system, system, dma_ports, ruby_system):
52
53 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
54 panic("This script requires the MOESI_CMP_directory protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 l2_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72 l2_bits = int(math.log(options.num_l2caches, 2))
73 block_size_bits = int(math.log(options.cacheline_size, 2))
74
75 for i in xrange(options.num_cpus):
76 #
77 # First create the Ruby objects associated with this cpu
78 #
79 l1i_cache = L1Cache(size = options.l1i_size,
80 assoc = options.l1i_assoc,
81 start_index_bit = block_size_bits,
82 is_icache = True)
83 l1d_cache = L1Cache(size = options.l1d_size,
84 assoc = options.l1d_assoc,
85 start_index_bit = block_size_bits,
86 is_icache = False)
87
88 l1_cntrl = L1Cache_Controller(version = i,
89 L1Icache = l1i_cache,
90 L1Dcache = l1d_cache,
91 l2_select_num_bits = l2_bits,
92 send_evictions = (
93 options.cpu_type == "detailed"),
94 transitions_per_cycle = options.ports,
95 clk_domain=system.cpu[i].clk_domain,
96 ruby_system = ruby_system)
97
98 cpu_seq = RubySequencer(version = i,
99 icache = l1i_cache,
100 dcache = l1d_cache,
101 clk_domain=system.cpu[i].clk_domain,
102 ruby_system = ruby_system)
103
104 l1_cntrl.sequencer = cpu_seq
105 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
106
107 # Add controllers and sequencers to the appropriate lists
108 cpu_sequencers.append(cpu_seq)
109 l1_cntrl_nodes.append(l1_cntrl)
110
111 # Connect the L1 controllers and the network
112 l1_cntrl.requestFromL1Cache = ruby_system.network.slave
113 l1_cntrl.responseFromL1Cache = ruby_system.network.slave
114 l1_cntrl.requestToL1Cache = ruby_system.network.master
115 l1_cntrl.responseToL1Cache = ruby_system.network.master
116
117
118 l2_index_start = block_size_bits + l2_bits
119
120 for i in xrange(options.num_l2caches):
121 #
122 # First create the Ruby objects associated with this cpu
123 #
124 l2_cache = L2Cache(size = options.l2_size,
125 assoc = options.l2_assoc,
126 start_index_bit = l2_index_start)
127
128 l2_cntrl = L2Cache_Controller(version = i,
129 L2cache = l2_cache,
130 transitions_per_cycle = options.ports,
131 ruby_system = ruby_system)
132
133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 # Connect the L2 controllers and the network
137 l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
138 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
139 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
140
141 l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
142 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
143 l2_cntrl.responseToL2Cache = ruby_system.network.master
144
145
146 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
147 assert(phys_mem_size % options.num_dirs == 0)
148 mem_module_size = phys_mem_size / options.num_dirs
149
150
151 # Run each of the ruby memory controllers at a ratio of the frequency of
152 # the ruby system.
153 # clk_divider value is a fix to pass regression.
154 ruby_system.memctrl_clk_domain = DerivedClockDomain(
155 clk_domain=ruby_system.clk_domain,
156 clk_divider=3)
157
158 for i in xrange(options.num_dirs):
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 3
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
51def create_system(options, full_system, system, dma_ports, ruby_system):
52
53 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
54 panic("This script requires the MOESI_CMP_directory protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 l2_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72 l2_bits = int(math.log(options.num_l2caches, 2))
73 block_size_bits = int(math.log(options.cacheline_size, 2))
74
75 for i in xrange(options.num_cpus):
76 #
77 # First create the Ruby objects associated with this cpu
78 #
79 l1i_cache = L1Cache(size = options.l1i_size,
80 assoc = options.l1i_assoc,
81 start_index_bit = block_size_bits,
82 is_icache = True)
83 l1d_cache = L1Cache(size = options.l1d_size,
84 assoc = options.l1d_assoc,
85 start_index_bit = block_size_bits,
86 is_icache = False)
87
88 l1_cntrl = L1Cache_Controller(version = i,
89 L1Icache = l1i_cache,
90 L1Dcache = l1d_cache,
91 l2_select_num_bits = l2_bits,
92 send_evictions = (
93 options.cpu_type == "detailed"),
94 transitions_per_cycle = options.ports,
95 clk_domain=system.cpu[i].clk_domain,
96 ruby_system = ruby_system)
97
98 cpu_seq = RubySequencer(version = i,
99 icache = l1i_cache,
100 dcache = l1d_cache,
101 clk_domain=system.cpu[i].clk_domain,
102 ruby_system = ruby_system)
103
104 l1_cntrl.sequencer = cpu_seq
105 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
106
107 # Add controllers and sequencers to the appropriate lists
108 cpu_sequencers.append(cpu_seq)
109 l1_cntrl_nodes.append(l1_cntrl)
110
111 # Connect the L1 controllers and the network
112 l1_cntrl.requestFromL1Cache = ruby_system.network.slave
113 l1_cntrl.responseFromL1Cache = ruby_system.network.slave
114 l1_cntrl.requestToL1Cache = ruby_system.network.master
115 l1_cntrl.responseToL1Cache = ruby_system.network.master
116
117
118 l2_index_start = block_size_bits + l2_bits
119
120 for i in xrange(options.num_l2caches):
121 #
122 # First create the Ruby objects associated with this cpu
123 #
124 l2_cache = L2Cache(size = options.l2_size,
125 assoc = options.l2_assoc,
126 start_index_bit = l2_index_start)
127
128 l2_cntrl = L2Cache_Controller(version = i,
129 L2cache = l2_cache,
130 transitions_per_cycle = options.ports,
131 ruby_system = ruby_system)
132
133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 # Connect the L2 controllers and the network
137 l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
138 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
139 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
140
141 l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
142 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
143 l2_cntrl.responseToL2Cache = ruby_system.network.master
144
145
146 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
147 assert(phys_mem_size % options.num_dirs == 0)
148 mem_module_size = phys_mem_size / options.num_dirs
149
150
151 # Run each of the ruby memory controllers at a ratio of the frequency of
152 # the ruby system.
153 # clk_divider value is a fix to pass regression.
154 ruby_system.memctrl_clk_domain = DerivedClockDomain(
155 clk_domain=ruby_system.clk_domain,
156 clk_divider=3)
157
158 for i in xrange(options.num_dirs):
|
177 transitions_per_cycle = options.ports,
178 ruby_system = ruby_system)
179
180 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
181 dir_cntrl_nodes.append(dir_cntrl)
182
183 # Connect the directory controllers and the network
184 dir_cntrl.requestToDir = ruby_system.network.master
185 dir_cntrl.responseToDir = ruby_system.network.master
186 dir_cntrl.responseFromDir = ruby_system.network.slave
187 dir_cntrl.forwardFromDir = ruby_system.network.slave
188
189
190 for i, dma_port in enumerate(dma_ports):
191 #
192 # Create the Ruby objects associated with the dma controller
193 #
194 dma_seq = DMASequencer(version = i,
195 ruby_system = ruby_system,
196 slave = dma_port)
197
198 dma_cntrl = DMA_Controller(version = i,
199 dma_sequencer = dma_seq,
200 transitions_per_cycle = options.ports,
201 ruby_system = ruby_system)
202
203 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
204 dma_cntrl_nodes.append(dma_cntrl)
205
206 # Connect the dma controller to the network
207 dma_cntrl.responseFromDir = ruby_system.network.master
208 dma_cntrl.reqToDir = ruby_system.network.slave
209 dma_cntrl.respToDir = ruby_system.network.slave
210
211
212 all_cntrls = l1_cntrl_nodes + \
213 l2_cntrl_nodes + \
214 dir_cntrl_nodes + \
215 dma_cntrl_nodes
216
217 # Create the io controller and the sequencer
218 if full_system:
219 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
220 ruby_system._io_port = io_seq
221 io_controller = DMA_Controller(version = len(dma_ports),
222 dma_sequencer = io_seq,
223 ruby_system = ruby_system)
224 ruby_system.io_controller = io_controller
225
226 # Connect the dma controller to the network
227 io_controller.responseFromDir = ruby_system.network.master
228 io_controller.reqToDir = ruby_system.network.slave
229 io_controller.respToDir = ruby_system.network.slave
230
231 all_cntrls = all_cntrls + [io_controller]
232
233
234 topology = create_topology(all_cntrls, options)
235 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 165 transitions_per_cycle = options.ports,
166 ruby_system = ruby_system)
167
168 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
169 dir_cntrl_nodes.append(dir_cntrl)
170
171 # Connect the directory controllers and the network
172 dir_cntrl.requestToDir = ruby_system.network.master
173 dir_cntrl.responseToDir = ruby_system.network.master
174 dir_cntrl.responseFromDir = ruby_system.network.slave
175 dir_cntrl.forwardFromDir = ruby_system.network.slave
176
177
178 for i, dma_port in enumerate(dma_ports):
179 #
180 # Create the Ruby objects associated with the dma controller
181 #
182 dma_seq = DMASequencer(version = i,
183 ruby_system = ruby_system,
184 slave = dma_port)
185
186 dma_cntrl = DMA_Controller(version = i,
187 dma_sequencer = dma_seq,
188 transitions_per_cycle = options.ports,
189 ruby_system = ruby_system)
190
191 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
192 dma_cntrl_nodes.append(dma_cntrl)
193
194 # Connect the dma controller to the network
195 dma_cntrl.responseFromDir = ruby_system.network.master
196 dma_cntrl.reqToDir = ruby_system.network.slave
197 dma_cntrl.respToDir = ruby_system.network.slave
198
199
200 all_cntrls = l1_cntrl_nodes + \
201 l2_cntrl_nodes + \
202 dir_cntrl_nodes + \
203 dma_cntrl_nodes
204
205 # Create the io controller and the sequencer
206 if full_system:
207 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
208 ruby_system._io_port = io_seq
209 io_controller = DMA_Controller(version = len(dma_ports),
210 dma_sequencer = io_seq,
211 ruby_system = ruby_system)
212 ruby_system.io_controller = io_controller
213
214 # Connect the dma controller to the network
215 io_controller.responseFromDir = ruby_system.network.master
216 io_controller.reqToDir = ruby_system.network.slave
217 io_controller.respToDir = ruby_system.network.slave
218
219 all_cntrls = all_cntrls + [io_controller]
220
221
222 topology = create_topology(all_cntrls, options)
223 return (cpu_sequencers, dir_cntrl_nodes, topology)
|