MOESI_CMP_directory.py (8717:5c253f1031d7) | MOESI_CMP_directory.py (8845:a230379caf65) |
---|---|
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 89 unchanged lines hidden (view full) --- 98 dcache = l1d_cache, 99 physMemPort = system.physmem.port, 100 physmem = system.physmem, 101 ruby_system = ruby_system) 102 103 l1_cntrl.sequencer = cpu_seq 104 105 if piobus != None: | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 89 unchanged lines hidden (view full) --- 98 dcache = l1d_cache, 99 physMemPort = system.physmem.port, 100 physmem = system.physmem, 101 ruby_system = ruby_system) 102 103 l1_cntrl.sequencer = cpu_seq 104 105 if piobus != None: |
106 cpu_seq.pio_port = piobus.port | 106 cpu_seq.pio_port = piobus.slave |
107 108 exec("system.l1_cntrl%d = l1_cntrl" % i) 109 # 110 # Add controllers and sequencers to the appropriate lists 111 # 112 cpu_sequencers.append(cpu_seq) 113 l1_cntrl_nodes.append(l1_cntrl) 114 --- 57 unchanged lines hidden (view full) --- 172 173 dma_cntrl = DMA_Controller(version = i, 174 cntrl_id = cntrl_count, 175 dma_sequencer = dma_seq, 176 ruby_system = ruby_system) 177 178 exec("system.dma_cntrl%d = dma_cntrl" % i) 179 if dma_device.type == 'MemTest': | 107 108 exec("system.l1_cntrl%d = l1_cntrl" % i) 109 # 110 # Add controllers and sequencers to the appropriate lists 111 # 112 cpu_sequencers.append(cpu_seq) 113 l1_cntrl_nodes.append(l1_cntrl) 114 --- 57 unchanged lines hidden (view full) --- 172 173 dma_cntrl = DMA_Controller(version = i, 174 cntrl_id = cntrl_count, 175 dma_sequencer = dma_seq, 176 ruby_system = ruby_system) 177 178 exec("system.dma_cntrl%d = dma_cntrl" % i) 179 if dma_device.type == 'MemTest': |
180 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) | 180 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i) |
181 else: | 181 else: |
182 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) | 182 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i) |
183 dma_cntrl_nodes.append(dma_cntrl) 184 185 cntrl_count += 1 186 187 all_cntrls = l1_cntrl_nodes + \ 188 l2_cntrl_nodes + \ 189 dir_cntrl_nodes + \ 190 dma_cntrl_nodes 191 192 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 183 dma_cntrl_nodes.append(dma_cntrl) 184 185 cntrl_count += 1 186 187 all_cntrls = l1_cntrl_nodes + \ 188 l2_cntrl_nodes + \ 189 dir_cntrl_nodes + \ 190 dma_cntrl_nodes 191 192 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |