1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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89
90 l1_cntrl = L1Cache_Controller(version = i,
91 cntrl_id = cntrl_count,
92 L1Icache = l1i_cache,
93 L1Dcache = l1d_cache,
94 l2_select_num_bits = l2_bits,
95 send_evictions = (
96 options.cpu_type == "detailed"),
97 ruby_system = ruby_system)
98
99 cpu_seq = RubySequencer(version = i,
100 icache = l1i_cache,
101 dcache = l1d_cache,
102 ruby_system = ruby_system)
103
104 l1_cntrl.sequencer = cpu_seq

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123 #
124 l2_cache = L2Cache(size = options.l2_size,
125 assoc = options.l2_assoc,
126 start_index_bit = l2_index_start)
127
128 l2_cntrl = L2Cache_Controller(version = i,
129 cntrl_id = cntrl_count,
130 L2cache = l2_cache,
131 ruby_system = ruby_system)
132
133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 cntrl_count += 1
137
138 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))

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161
162 dir_cntrl = Directory_Controller(version = i,
163 cntrl_id = cntrl_count,
164 directory = \
165 RubyDirectoryMemory(version = i,
166 size = dir_size,
167 use_map = options.use_map),
168 memBuffer = mem_cntrl,
169 ruby_system = ruby_system)
170
171 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
172 dir_cntrl_nodes.append(dir_cntrl)
173
174 cntrl_count += 1
175
176 for i, dma_port in enumerate(dma_ports):
177 #
178 # Create the Ruby objects associated with the dma controller
179 #
180 dma_seq = DMASequencer(version = i,
181 ruby_system = ruby_system)
182
183 dma_cntrl = DMA_Controller(version = i,
184 cntrl_id = cntrl_count,
185 dma_sequencer = dma_seq,
186 ruby_system = ruby_system)
187
188 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
189 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
190 dma_cntrl_nodes.append(dma_cntrl)
191 cntrl_count += 1
192
193 all_cntrls = l1_cntrl_nodes + \
194 l2_cntrl_nodes + \
195 dir_cntrl_nodes + \
196 dma_cntrl_nodes
197
198 topology = create_topology(all_cntrls, options)
199
200 return (cpu_sequencers, dir_cntrl_nodes, topology)