1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39 latency = 3
40
41#

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177 dma_cntrl_nodes.append(dma_cntrl)
178 cntrl_count += 1
179
180 all_cntrls = l1_cntrl_nodes + \
181 l2_cntrl_nodes + \
182 dir_cntrl_nodes + \
183 dma_cntrl_nodes
184
185 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)