1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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98 l1_cntrl.sequencer = cpu_seq
99 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
100
101 # Add controllers and sequencers to the appropriate lists
102 cpu_sequencers.append(cpu_seq)
103 l1_cntrl_nodes.append(l1_cntrl)
104
105 # Connect the L1 controllers and the network
106 l1_cntrl.requestFromL1Cache = ruby_system.network.slave
107 l1_cntrl.responseFromL1Cache = ruby_system.network.slave
108 l1_cntrl.requestToL1Cache = ruby_system.network.master
109 l1_cntrl.responseToL1Cache = ruby_system.network.master
110
111
112 l2_index_start = block_size_bits + l2_bits
113
114 for i in xrange(options.num_l2caches):
115 #
116 # First create the Ruby objects associated with this cpu
117 #

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123 L2cache = l2_cache,
124 transitions_per_cycle = options.ports,
125 ruby_system = ruby_system)
126
127 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
128 l2_cntrl_nodes.append(l2_cntrl)
129
130 # Connect the L2 controllers and the network
131 l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
132 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
133 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
134
135 l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
136 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
137 l2_cntrl.responseToL2Cache = ruby_system.network.master
138
139
140 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
141 assert(phys_mem_size % options.num_dirs == 0)
142 mem_module_size = phys_mem_size / options.num_dirs
143
144
145 # Run each of the ruby memory controllers at a ratio of the frequency of

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158 version = i, size = dir_size),
159 transitions_per_cycle = options.ports,
160 ruby_system = ruby_system)
161
162 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
163 dir_cntrl_nodes.append(dir_cntrl)
164
165 # Connect the directory controllers and the network
166 dir_cntrl.requestToDir = ruby_system.network.master
167 dir_cntrl.responseToDir = ruby_system.network.master
168 dir_cntrl.responseFromDir = ruby_system.network.slave
169 dir_cntrl.forwardFromDir = ruby_system.network.slave
170
171
172 for i, dma_port in enumerate(dma_ports):
173 #
174 # Create the Ruby objects associated with the dma controller
175 #
176 dma_seq = DMASequencer(version = i,
177 ruby_system = ruby_system,
178 slave = dma_port)
179
180 dma_cntrl = DMA_Controller(version = i,
181 dma_sequencer = dma_seq,
182 transitions_per_cycle = options.ports,
183 ruby_system = ruby_system)
184
185 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
186 dma_cntrl_nodes.append(dma_cntrl)
187
188 # Connect the dma controller to the network
189 dma_cntrl.responseFromDir = ruby_system.network.master
190 dma_cntrl.reqToDir = ruby_system.network.slave
191 dma_cntrl.respToDir = ruby_system.network.slave
192
193
194 all_cntrls = l1_cntrl_nodes + \
195 l2_cntrl_nodes + \
196 dir_cntrl_nodes + \
197 dma_cntrl_nodes
198
199 # Create the io controller and the sequencer
200 if full_system:
201 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
202 ruby_system._io_port = io_seq
203 io_controller = DMA_Controller(version = len(dma_ports),
204 dma_sequencer = io_seq,
205 ruby_system = ruby_system)
206 ruby_system.io_controller = io_controller
207
208 # Connect the dma controller to the network
209 io_controller.responseFromDir = ruby_system.network.master
210 io_controller.reqToDir = ruby_system.network.slave
211 io_controller.respToDir = ruby_system.network.slave
212
213 all_cntrls = all_cntrls + [io_controller]
214
215
216 topology = create_topology(all_cntrls, options)
217 return (cpu_sequencers, dir_cntrl_nodes, topology)