1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 15
47
48def define_options(parser):
49 return
50
51def create_system(options, system, dma_ports, ruby_system):
52
53 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
54 panic("This script requires the MOESI_CMP_directory protocol to be built.")
55
56 cpu_sequencers = []
57
58 #
59 # The ruby network creation expects the list of nodes in the system to be

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187 dir_cntrl.forwardFromDir = ruby_system.network.slave
188
189
190 for i, dma_port in enumerate(dma_ports):
191 #
192 # Create the Ruby objects associated with the dma controller
193 #
194 dma_seq = DMASequencer(version = i,
195 ruby_system = ruby_system)
196
197 dma_cntrl = DMA_Controller(version = i,
198 dma_sequencer = dma_seq,
199 transitions_per_cycle = options.ports,
200 ruby_system = ruby_system)
201
202 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
203 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
204 dma_cntrl_nodes.append(dma_cntrl)
205
206
207 all_cntrls = l1_cntrl_nodes + \
208 l2_cntrl_nodes + \
209 dir_cntrl_nodes + \
210 dma_cntrl_nodes
211
212 topology = create_topology(all_cntrls, options)
213 return (cpu_sequencers, dir_cntrl_nodes, topology)