1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 121 unchanged lines hidden (view full) ---

130 L2cache = l2_cache,
131 ruby_system = ruby_system)
132
133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 cntrl_count += 1
137
138 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
139 assert(phys_mem_size % options.num_dirs == 0)
140 mem_module_size = phys_mem_size / options.num_dirs
141
142 # Run each of the ruby memory controllers at a ratio of the frequency of
143 # the ruby system.
144 # clk_divider value is a fix to pass regression.
145 ruby_system.memctrl_clk_domain = DerivedClockDomain(
146 clk_domain=ruby_system.clk_domain,

--- 54 unchanged lines hidden ---