1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 89 unchanged lines hidden (view full) ---

98 l1_cntrl.sequencer = cpu_seq
99 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
100
101 # Add controllers and sequencers to the appropriate lists
102 cpu_sequencers.append(cpu_seq)
103 l1_cntrl_nodes.append(l1_cntrl)
104
105 # Connect the L1 controllers and the network
106 l1_cntrl.mandatoryQueue = MessageBuffer()
107 l1_cntrl.requestFromL1Cache = MessageBuffer()
108 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
109 l1_cntrl.responseFromL1Cache = MessageBuffer()
110 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
111 l1_cntrl.requestToL1Cache = MessageBuffer()
112 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
113 l1_cntrl.responseToL1Cache = MessageBuffer()
114 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
115 l1_cntrl.triggerQueue = MessageBuffer(ordered = True)
116
117
118 l2_index_start = block_size_bits + l2_bits
119
120 for i in xrange(options.num_l2caches):
121 #
122 # First create the Ruby objects associated with this cpu
123 #

--- 5 unchanged lines hidden (view full) ---

129 L2cache = l2_cache,
130 transitions_per_cycle = options.ports,
131 ruby_system = ruby_system)
132
133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
134 l2_cntrl_nodes.append(l2_cntrl)
135
136 # Connect the L2 controllers and the network
137 l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
138 l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
139 l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
140 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
141 l2_cntrl.responseFromL2Cache = MessageBuffer()
142 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
143
144 l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
145 l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
146 l2_cntrl.L1RequestToL2Cache = MessageBuffer()
147 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
148 l2_cntrl.responseToL2Cache = MessageBuffer()
149 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
150 l2_cntrl.triggerQueue = MessageBuffer(ordered = True)
151
152
153 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
154 assert(phys_mem_size % options.num_dirs == 0)
155 mem_module_size = phys_mem_size / options.num_dirs
156
157
158 # Run each of the ruby memory controllers at a ratio of the frequency of

--- 12 unchanged lines hidden (view full) ---

171 version = i, size = dir_size),
172 transitions_per_cycle = options.ports,
173 ruby_system = ruby_system)
174
175 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
176 dir_cntrl_nodes.append(dir_cntrl)
177
178 # Connect the directory controllers and the network
179 dir_cntrl.requestToDir = MessageBuffer()
180 dir_cntrl.requestToDir.slave = ruby_system.network.master
181 dir_cntrl.responseToDir = MessageBuffer()
182 dir_cntrl.responseToDir.slave = ruby_system.network.master
183 dir_cntrl.responseFromDir = MessageBuffer()
184 dir_cntrl.responseFromDir.master = ruby_system.network.slave
185 dir_cntrl.forwardFromDir = MessageBuffer()
186 dir_cntrl.forwardFromDir.master = ruby_system.network.slave
187 dir_cntrl.responseFromMemory = MessageBuffer()
188
189
190 for i, dma_port in enumerate(dma_ports):
191 #
192 # Create the Ruby objects associated with the dma controller
193 #
194 dma_seq = DMASequencer(version = i,
195 ruby_system = ruby_system,
196 slave = dma_port)
197
198 dma_cntrl = DMA_Controller(version = i,
199 dma_sequencer = dma_seq,
200 transitions_per_cycle = options.ports,
201 ruby_system = ruby_system)
202
203 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
204 dma_cntrl_nodes.append(dma_cntrl)
205
206 # Connect the dma controller to the network
207 dma_cntrl.mandatoryQueue = MessageBuffer()
208 dma_cntrl.responseFromDir = MessageBuffer()
209 dma_cntrl.responseFromDir.slave = ruby_system.network.master
210 dma_cntrl.reqToDir = MessageBuffer()
211 dma_cntrl.reqToDir.master = ruby_system.network.slave
212 dma_cntrl.respToDir = MessageBuffer()
213 dma_cntrl.respToDir.master = ruby_system.network.slave
214 dma_cntrl.triggerQueue = MessageBuffer(ordered = True)
215
216
217 all_cntrls = l1_cntrl_nodes + \
218 l2_cntrl_nodes + \
219 dir_cntrl_nodes + \
220 dma_cntrl_nodes
221
222 # Create the io controller and the sequencer
223 if full_system:
224 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
225 ruby_system._io_port = io_seq
226 io_controller = DMA_Controller(version = len(dma_ports),
227 dma_sequencer = io_seq,
228 ruby_system = ruby_system)
229 ruby_system.io_controller = io_controller
230
231 # Connect the dma controller to the network
232 io_controller.mandatoryQueue = MessageBuffer()
233 io_controller.responseFromDir = MessageBuffer()
234 io_controller.responseFromDir.slave = ruby_system.network.master
235 io_controller.reqToDir = MessageBuffer()
236 io_controller.reqToDir.master = ruby_system.network.slave
237 io_controller.respToDir = MessageBuffer()
238 io_controller.respToDir.master = ruby_system.network.slave
239 io_controller.triggerQueue = MessageBuffer(ordered = True)
240
241 all_cntrls = all_cntrls + [io_controller]
242
243
244 topology = create_topology(all_cntrls, options)
245 return (cpu_sequencers, dir_cntrl_nodes, topology)