| MOESI_AMD_Base.py (13400:cf74d21e948f) | MOESI_AMD_Base.py (13731:67cd980cb20f) |
|---|---|
| 1# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# For use for simulation and test purposes only 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are met: 8# --- 234 unchanged lines hidden (view full) --- 243 else: 244 # if the numa_bit is not specified, set the directory bits as the 245 # lowest bits above the block offset bits, and the numa_bit as the 246 # highest of those directory bits 247 dir_bits = int(math.log(options.num_dirs, 2)) 248 block_size_bits = int(math.log(options.cacheline_size, 2)) 249 numa_bit = block_size_bits + dir_bits - 1 250 | 1# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# For use for simulation and test purposes only 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are met: 8# --- 234 unchanged lines hidden (view full) --- 243 else: 244 # if the numa_bit is not specified, set the directory bits as the 245 # lowest bits above the block offset bits, and the numa_bit as the 246 # highest of those directory bits 247 dir_bits = int(math.log(options.num_dirs, 2)) 248 block_size_bits = int(math.log(options.cacheline_size, 2)) 249 numa_bit = block_size_bits + dir_bits - 1 250 |
| 251 for i in xrange(options.num_dirs): | 251 for i in range(options.num_dirs): |
| 252 dir_ranges = [] 253 for r in system.mem_ranges: 254 addr_range = m5.objects.AddrRange(r.start, size = r.size(), 255 intlvHighBit = numa_bit, 256 intlvBits = dir_bits, 257 intlvMatch = i) 258 dir_ranges.append(addr_range) 259 --- 29 unchanged lines hidden (view full) --- 289 # Technically this config can support an odd number of cpus, but the top 290 # level config files, such as the ruby_random_tester, will get confused if 291 # the number of cpus does not equal the number of sequencers. Thus make 292 # sure that an even number of cpus is specified. 293 assert((options.num_cpus % 2) == 0) 294 295 # For an odd number of CPUs, still create the right number of controllers 296 cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s | 252 dir_ranges = [] 253 for r in system.mem_ranges: 254 addr_range = m5.objects.AddrRange(r.start, size = r.size(), 255 intlvHighBit = numa_bit, 256 intlvBits = dir_bits, 257 intlvMatch = i) 258 dir_ranges.append(addr_range) 259 --- 29 unchanged lines hidden (view full) --- 289 # Technically this config can support an odd number of cpus, but the top 290 # level config files, such as the ruby_random_tester, will get confused if 291 # the number of cpus does not equal the number of sequencers. Thus make 292 # sure that an even number of cpus is specified. 293 assert((options.num_cpus % 2) == 0) 294 295 # For an odd number of CPUs, still create the right number of controllers 296 cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s |
| 297 for i in xrange((options.num_cpus + 1) / 2): | 297 for i in range((options.num_cpus + 1) // 2): |
| 298 299 cp_cntrl = CPCntrl() 300 cp_cntrl.create(options, ruby_system, system) 301 302 exec("system.cp_cntrl%d = cp_cntrl" % i) 303 # 304 # Add controllers and sequencers to the appropriate lists 305 # --- 32 unchanged lines hidden --- | 298 299 cp_cntrl = CPCntrl() 300 cp_cntrl.create(options, ruby_system, system) 301 302 exec("system.cp_cntrl%d = cp_cntrl" % i) 303 # 304 # Add controllers and sequencers to the appropriate lists 305 # --- 32 unchanged lines hidden --- |