| MOESI_AMD_Base.py (11670:6ce719503eae) | MOESI_AMD_Base.py (12065:e3e51756dfef) |
|---|---|
| 1# 2# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# For use for simulation and test purposes only 6# 7# Redistribution and use in source and binary forms, with or without 8# modification, are permitted provided that the following conditions are met: --- 152 unchanged lines hidden (view full) --- 161 req_to_l3, probe_to_l3, resp_to_l3): 162 self.reqToDir = req_to_dir 163 self.respToDir = resp_to_dir 164 self.l3UnblockToDir = l3_unblock_to_dir 165 self.reqToL3 = req_to_l3 166 self.probeToL3 = probe_to_l3 167 self.respToL3 = resp_to_l3 168 | 1# 2# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# For use for simulation and test purposes only 6# 7# Redistribution and use in source and binary forms, with or without 8# modification, are permitted provided that the following conditions are met: --- 152 unchanged lines hidden (view full) --- 161 req_to_l3, probe_to_l3, resp_to_l3): 162 self.reqToDir = req_to_dir 163 self.respToDir = resp_to_dir 164 self.l3UnblockToDir = l3_unblock_to_dir 165 self.reqToL3 = req_to_l3 166 self.probeToL3 = probe_to_l3 167 self.respToL3 = resp_to_l3 168 |
| 169class DirMem(RubyDirectoryMemory, CntrlBase): 170 def create(self, options, ruby_system, system): 171 self.version = self.versionCount() 172 173 phys_mem_size = AddrRange(options.mem_size).size() 174 mem_module_size = phys_mem_size / options.num_dirs 175 dir_size = MemorySize('0B') 176 dir_size.value = mem_module_size 177 self.size = dir_size 178 | |
| 179class DirCntrl(Directory_Controller, CntrlBase): | 169class DirCntrl(Directory_Controller, CntrlBase): |
| 180 def create(self, options, ruby_system, system): | 170 def create(self, options, dir_ranges, ruby_system, system): |
| 181 self.version = self.versionCount() 182 183 self.response_latency = 30 184 | 171 self.version = self.versionCount() 172 173 self.response_latency = 30 174 |
| 185 self.directory = DirMem() 186 self.directory.create(options, ruby_system, system) | 175 self.addr_ranges = dir_ranges 176 self.directory = RubyDirectoryMemory() |
| 187 188 self.L3CacheMemory = L3Cache() 189 self.L3CacheMemory.create(options, ruby_system, system) 190 191 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 192 self.L3CacheMemory.tagAccessLatency) 193 194 self.number_of_TBEs = options.num_tbes --- 45 unchanged lines hidden (view full) --- 240 # 241 # Must create the individual controllers before the network to ensure 242 # the controller constructors are called before the network constructor 243 # 244 245 # This is the base crossbar that connects the L3s, Dirs, and cpu 246 # Cluster 247 mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s | 177 178 self.L3CacheMemory = L3Cache() 179 self.L3CacheMemory.create(options, ruby_system, system) 180 181 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 182 self.L3CacheMemory.tagAccessLatency) 183 184 self.number_of_TBEs = options.num_tbes --- 45 unchanged lines hidden (view full) --- 230 # 231 # Must create the individual controllers before the network to ensure 232 # the controller constructors are called before the network constructor 233 # 234 235 # This is the base crossbar that connects the L3s, Dirs, and cpu 236 # Cluster 237 mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s |
| 238 239 if options.numa_high_bit: 240 numa_bit = options.numa_high_bit 241 else: 242 # if the numa_bit is not specified, set the directory bits as the 243 # lowest bits above the block offset bits, and the numa_bit as the 244 # highest of those directory bits 245 dir_bits = int(math.log(options.num_dirs, 2)) 246 block_size_bits = int(math.log(options.cacheline_size, 2)) 247 numa_bit = block_size_bits + dir_bits - 1 248 |
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| 248 for i in xrange(options.num_dirs): | 249 for i in xrange(options.num_dirs): |
| 250 dir_ranges = [] 251 for r in system.mem_ranges: 252 addr_range = m5.objects.AddrRange(r.start, size = r.size(), 253 intlvHighBit = numa_bit, 254 intlvBits = dir_bits, 255 intlvMatch = i) 256 dir_ranges.append(addr_range) |
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| 249 | 257 |
| 258 |
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| 250 dir_cntrl = DirCntrl(TCC_select_num_bits = 0) | 259 dir_cntrl = DirCntrl(TCC_select_num_bits = 0) |
| 251 dir_cntrl.create(options, ruby_system, system) | 260 dir_cntrl.create(options, dir_ranges, ruby_system, system) |
| 252 253 # Connect the Directory controller to the ruby network 254 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 255 dir_cntrl.requestFromCores.slave = ruby_system.network.master 256 257 dir_cntrl.responseFromCores = MessageBuffer() 258 dir_cntrl.responseFromCores.slave = ruby_system.network.master 259 --- 67 unchanged lines hidden --- | 261 262 # Connect the Directory controller to the ruby network 263 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 264 dir_cntrl.requestFromCores.slave = ruby_system.network.master 265 266 dir_cntrl.responseFromCores = MessageBuffer() 267 dir_cntrl.responseFromCores.slave = ruby_system.network.master 268 --- 67 unchanged lines hidden --- |