1# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#
9# 1. Redistributions of source code must retain the above copyright notice,
10# this list of conditions and the following disclaimer.
11#
12# 2. Redistributions in binary form must reproduce the above copyright notice,
13# this list of conditions and the following disclaimer in the documentation
14# and/or other materials provided with the distribution.
15#
16# 3. Neither the name of the copyright holder nor the names of its
17# contributors may be used to endorse or promote products derived from this
18# software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30# POSSIBILITY OF SUCH DAMAGE.
31#
32# Authors: Lisa Hsu
33
34import math
35import m5
36from m5.objects import *
37from m5.defines import buildEnv
38from m5.util import addToPath
39from Ruby import create_topology
40from Ruby import send_evicts
| 1# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#
9# 1. Redistributions of source code must retain the above copyright notice,
10# this list of conditions and the following disclaimer.
11#
12# 2. Redistributions in binary form must reproduce the above copyright notice,
13# this list of conditions and the following disclaimer in the documentation
14# and/or other materials provided with the distribution.
15#
16# 3. Neither the name of the copyright holder nor the names of its
17# contributors may be used to endorse or promote products derived from this
18# software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30# POSSIBILITY OF SUCH DAMAGE.
31#
32# Authors: Lisa Hsu
33
34import math
35import m5
36from m5.objects import *
37from m5.defines import buildEnv
38from m5.util import addToPath
39from Ruby import create_topology
40from Ruby import send_evicts
|
42
43addToPath('../')
44
45from topologies.Cluster import Cluster
46from topologies.Crossbar import Crossbar
47
48class CntrlBase:
49 _seqs = 0
50 @classmethod
51 def seqCount(cls):
52 # Use SeqCount not class since we need global count
53 CntrlBase._seqs += 1
54 return CntrlBase._seqs - 1
55
56 _cntrls = 0
57 @classmethod
58 def cntrlCount(cls):
59 # Use CntlCount not class since we need global count
60 CntrlBase._cntrls += 1
61 return CntrlBase._cntrls - 1
62
63 _version = 0
64 @classmethod
65 def versionCount(cls):
66 cls._version += 1 # Use count for this particular type
67 return cls._version - 1
68
69class L1DCache(RubyCache):
70 resourceStalls = False
71 def create(self, options):
72 self.size = MemorySize(options.l1d_size)
73 self.assoc = options.l1d_assoc
74 self.replacement_policy = PseudoLRUReplacementPolicy()
75
76class L1ICache(RubyCache):
77 resourceStalls = False
78 def create(self, options):
79 self.size = MemorySize(options.l1i_size)
80 self.assoc = options.l1i_assoc
81 self.replacement_policy = PseudoLRUReplacementPolicy()
82
83class L2Cache(RubyCache):
84 resourceStalls = False
85 def create(self, options):
86 self.size = MemorySize(options.l2_size)
87 self.assoc = options.l2_assoc
88 self.replacement_policy = PseudoLRUReplacementPolicy()
89
90class CPCntrl(CorePair_Controller, CntrlBase):
91
92 def create(self, options, ruby_system, system):
93 self.version = self.versionCount()
94
95 self.L1Icache = L1ICache()
96 self.L1Icache.create(options)
97 self.L1D0cache = L1DCache()
98 self.L1D0cache.create(options)
99 self.L1D1cache = L1DCache()
100 self.L1D1cache.create(options)
101 self.L2cache = L2Cache()
102 self.L2cache.create(options)
103
104 self.sequencer = RubySequencer()
105 self.sequencer.icache_hit_latency = 2
106 self.sequencer.dcache_hit_latency = 2
107 self.sequencer.version = self.seqCount()
108 self.sequencer.icache = self.L1Icache
109 self.sequencer.dcache = self.L1D0cache
110 self.sequencer.ruby_system = ruby_system
111 self.sequencer.coreid = 0
112 self.sequencer.is_cpu_sequencer = True
113
114 self.sequencer1 = RubySequencer()
115 self.sequencer1.version = self.seqCount()
116 self.sequencer1.icache = self.L1Icache
117 self.sequencer1.dcache = self.L1D1cache
118 self.sequencer1.icache_hit_latency = 2
119 self.sequencer1.dcache_hit_latency = 2
120 self.sequencer1.ruby_system = ruby_system
121 self.sequencer1.coreid = 1
122 self.sequencer1.is_cpu_sequencer = True
123
124 self.issue_latency = options.cpu_to_dir_latency
125 self.send_evictions = send_evicts(options)
126
127 self.ruby_system = ruby_system
128
129 if options.recycle_latency:
130 self.recycle_latency = options.recycle_latency
131
132class L3Cache(RubyCache):
133 assoc = 8
134 dataArrayBanks = 256
135 tagArrayBanks = 256
136
137 def create(self, options, ruby_system, system):
138 self.size = MemorySize(options.l3_size)
139 self.size.value /= options.num_dirs
140 self.dataArrayBanks /= options.num_dirs
141 self.tagArrayBanks /= options.num_dirs
142 self.dataArrayBanks /= options.num_dirs
143 self.tagArrayBanks /= options.num_dirs
144 self.dataAccessLatency = options.l3_data_latency
145 self.tagAccessLatency = options.l3_tag_latency
146 self.resourceStalls = options.no_resource_stalls
147 self.replacement_policy = PseudoLRUReplacementPolicy()
148
149class L3Cntrl(L3Cache_Controller, CntrlBase):
150 def create(self, options, ruby_system, system):
151 self.version = self.versionCount()
152 self.L3cache = L3Cache()
153 self.L3cache.create(options, ruby_system, system)
154
155 self.l3_response_latency = max(self.L3cache.dataAccessLatency,
156 self.L3cache.tagAccessLatency)
157 self.ruby_system = ruby_system
158
159 if options.recycle_latency:
160 self.recycle_latency = options.recycle_latency
161
162 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
163 req_to_l3, probe_to_l3, resp_to_l3):
164 self.reqToDir = req_to_dir
165 self.respToDir = resp_to_dir
166 self.l3UnblockToDir = l3_unblock_to_dir
167 self.reqToL3 = req_to_l3
168 self.probeToL3 = probe_to_l3
169 self.respToL3 = resp_to_l3
170
171class DirCntrl(Directory_Controller, CntrlBase):
172 def create(self, options, dir_ranges, ruby_system, system):
173 self.version = self.versionCount()
174
175 self.response_latency = 30
176
177 self.addr_ranges = dir_ranges
178 self.directory = RubyDirectoryMemory()
179
180 self.L3CacheMemory = L3Cache()
181 self.L3CacheMemory.create(options, ruby_system, system)
182
183 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency,
184 self.L3CacheMemory.tagAccessLatency)
185
186 self.number_of_TBEs = options.num_tbes
187
188 self.ruby_system = ruby_system
189
190 if options.recycle_latency:
191 self.recycle_latency = options.recycle_latency
192
193 self.CPUonly = True
194
195 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
196 req_to_l3, probe_to_l3, resp_to_l3):
197 self.reqToDir = req_to_dir
198 self.respToDir = resp_to_dir
199 self.l3UnblockToDir = l3_unblock_to_dir
200 self.reqToL3 = req_to_l3
201 self.probeToL3 = probe_to_l3
202 self.respToL3 = resp_to_l3
203
204def define_options(parser):
205 parser.add_option("--num-subcaches", type="int", default=4)
206 parser.add_option("--l3-data-latency", type="int", default=20)
207 parser.add_option("--l3-tag-latency", type="int", default=15)
208 parser.add_option("--cpu-to-dir-latency", type="int", default=15)
209 parser.add_option("--no-resource-stalls", action="store_false",
210 default=True)
211 parser.add_option("--num-tbes", type="int", default=256)
212 parser.add_option("--l2-latency", type="int", default=50) # load to use
213
214def create_system(options, full_system, system, dma_devices, bootmem,
215 ruby_system):
216 if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base':
217 panic("This script requires the MOESI_AMD_Base protocol.")
218
219 cpu_sequencers = []
220
221 #
222 # The ruby network creation expects the list of nodes in the system to
223 # be consistent with the NetDest list. Therefore the l1 controller
224 # nodes must be listed before the directory nodes and directory nodes
225 # before dma nodes, etc.
226 #
227 l1_cntrl_nodes = []
228 l3_cntrl_nodes = []
229 dir_cntrl_nodes = []
230
231 control_count = 0
232
233 #
234 # Must create the individual controllers before the network to ensure
235 # the controller constructors are called before the network constructor
236 #
237
238 # This is the base crossbar that connects the L3s, Dirs, and cpu
239 # Cluster
240 mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
241
242 if options.numa_high_bit:
243 numa_bit = options.numa_high_bit
244 else:
245 # if the numa_bit is not specified, set the directory bits as the
246 # lowest bits above the block offset bits, and the numa_bit as the
247 # highest of those directory bits
248 dir_bits = int(math.log(options.num_dirs, 2))
249 block_size_bits = int(math.log(options.cacheline_size, 2))
250 numa_bit = block_size_bits + dir_bits - 1
251
252 for i in range(options.num_dirs):
253 dir_ranges = []
254 for r in system.mem_ranges:
255 addr_range = m5.objects.AddrRange(r.start, size = r.size(),
256 intlvHighBit = numa_bit,
257 intlvBits = dir_bits,
258 intlvMatch = i)
259 dir_ranges.append(addr_range)
260
261
262 dir_cntrl = DirCntrl(TCC_select_num_bits = 0)
263 dir_cntrl.create(options, dir_ranges, ruby_system, system)
264
265 # Connect the Directory controller to the ruby network
266 dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
267 dir_cntrl.requestFromCores.slave = ruby_system.network.master
268
269 dir_cntrl.responseFromCores = MessageBuffer()
270 dir_cntrl.responseFromCores.slave = ruby_system.network.master
271
272 dir_cntrl.unblockFromCores = MessageBuffer()
273 dir_cntrl.unblockFromCores.slave = ruby_system.network.master
274
275 dir_cntrl.probeToCore = MessageBuffer()
276 dir_cntrl.probeToCore.master = ruby_system.network.slave
277
278 dir_cntrl.responseToCore = MessageBuffer()
279 dir_cntrl.responseToCore.master = ruby_system.network.slave
280
281 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
282 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
283 dir_cntrl.responseFromMemory = MessageBuffer()
284
285 exec("system.dir_cntrl%d = dir_cntrl" % i)
286 dir_cntrl_nodes.append(dir_cntrl)
287
288 mainCluster.add(dir_cntrl)
289
290 # Technically this config can support an odd number of cpus, but the top
291 # level config files, such as the ruby_random_tester, will get confused if
292 # the number of cpus does not equal the number of sequencers. Thus make
293 # sure that an even number of cpus is specified.
294 assert((options.num_cpus % 2) == 0)
295
296 # For an odd number of CPUs, still create the right number of controllers
297 cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
298 for i in range((options.num_cpus + 1) // 2):
299
300 cp_cntrl = CPCntrl()
301 cp_cntrl.create(options, ruby_system, system)
302
303 exec("system.cp_cntrl%d = cp_cntrl" % i)
304 #
305 # Add controllers and sequencers to the appropriate lists
306 #
307 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
308
309 # Connect the CP controllers and the network
310 cp_cntrl.requestFromCore = MessageBuffer()
311 cp_cntrl.requestFromCore.master = ruby_system.network.slave
312
313 cp_cntrl.responseFromCore = MessageBuffer()
314 cp_cntrl.responseFromCore.master = ruby_system.network.slave
315
316 cp_cntrl.unblockFromCore = MessageBuffer()
317 cp_cntrl.unblockFromCore.master = ruby_system.network.slave
318
319 cp_cntrl.probeToCore = MessageBuffer()
320 cp_cntrl.probeToCore.slave = ruby_system.network.master
321
322 cp_cntrl.responseToCore = MessageBuffer()
323 cp_cntrl.responseToCore.slave = ruby_system.network.master
324
325 cp_cntrl.mandatoryQueue = MessageBuffer()
326 cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
327
328 cpuCluster.add(cp_cntrl)
329
330 # Register CPUs and caches for each CorePair and directory (SE mode only)
331 if not full_system:
332 FileSystemConfig.config_filesystem(options)
333 for i in xrange((options.num_cpus + 1) // 2):
334 FileSystemConfig.register_cpu(physical_package_id = 0,
335 core_siblings =
336 xrange(options.num_cpus),
337 core_id = i*2,
338 thread_siblings = [])
339
340 FileSystemConfig.register_cpu(physical_package_id = 0,
341 core_siblings =
342 xrange(options.num_cpus),
343 core_id = i*2+1,
344 thread_siblings = [])
345
346 FileSystemConfig.register_cache(level = 0,
347 idu_type = 'Instruction',
348 size = options.l1i_size,
349 line_size = options.cacheline_size,
350 assoc = options.l1i_assoc,
351 cpus = [i*2, i*2+1])
352
353 FileSystemConfig.register_cache(level = 0,
354 idu_type = 'Data',
355 size = options.l1d_size,
356 line_size = options.cacheline_size,
357 assoc = options.l1d_assoc,
358 cpus = [i*2])
359
360 FileSystemConfig.register_cache(level = 0,
361 idu_type = 'Data',
362 size = options.l1d_size,
363 line_size = options.cacheline_size,
364 assoc = options.l1d_assoc,
365 cpus = [i*2+1])
366
367 FileSystemConfig.register_cache(level = 1,
368 idu_type = 'Unified',
369 size = options.l2_size,
370 line_size = options.cacheline_size,
371 assoc = options.l2_assoc,
372 cpus = [i*2, i*2+1])
373
374 for i in range(options.num_dirs):
375 FileSystemConfig.register_cache(level = 2,
376 idu_type = 'Unified',
377 size = options.l3_size,
378 line_size = options.cacheline_size,
379 assoc = options.l3_assoc,
380 cpus = [n for n in
381 xrange(options.num_cpus)])
382
383 # Assuming no DMA devices
384 assert(len(dma_devices) == 0)
385
386 # Add cpu/gpu clusters to main cluster
387 mainCluster.add(cpuCluster)
388
389 ruby_system.network.number_of_virtual_networks = 10
390
391 return (cpu_sequencers, dir_cntrl_nodes, mainCluster)
| 42
43addToPath('../')
44
45from topologies.Cluster import Cluster
46from topologies.Crossbar import Crossbar
47
48class CntrlBase:
49 _seqs = 0
50 @classmethod
51 def seqCount(cls):
52 # Use SeqCount not class since we need global count
53 CntrlBase._seqs += 1
54 return CntrlBase._seqs - 1
55
56 _cntrls = 0
57 @classmethod
58 def cntrlCount(cls):
59 # Use CntlCount not class since we need global count
60 CntrlBase._cntrls += 1
61 return CntrlBase._cntrls - 1
62
63 _version = 0
64 @classmethod
65 def versionCount(cls):
66 cls._version += 1 # Use count for this particular type
67 return cls._version - 1
68
69class L1DCache(RubyCache):
70 resourceStalls = False
71 def create(self, options):
72 self.size = MemorySize(options.l1d_size)
73 self.assoc = options.l1d_assoc
74 self.replacement_policy = PseudoLRUReplacementPolicy()
75
76class L1ICache(RubyCache):
77 resourceStalls = False
78 def create(self, options):
79 self.size = MemorySize(options.l1i_size)
80 self.assoc = options.l1i_assoc
81 self.replacement_policy = PseudoLRUReplacementPolicy()
82
83class L2Cache(RubyCache):
84 resourceStalls = False
85 def create(self, options):
86 self.size = MemorySize(options.l2_size)
87 self.assoc = options.l2_assoc
88 self.replacement_policy = PseudoLRUReplacementPolicy()
89
90class CPCntrl(CorePair_Controller, CntrlBase):
91
92 def create(self, options, ruby_system, system):
93 self.version = self.versionCount()
94
95 self.L1Icache = L1ICache()
96 self.L1Icache.create(options)
97 self.L1D0cache = L1DCache()
98 self.L1D0cache.create(options)
99 self.L1D1cache = L1DCache()
100 self.L1D1cache.create(options)
101 self.L2cache = L2Cache()
102 self.L2cache.create(options)
103
104 self.sequencer = RubySequencer()
105 self.sequencer.icache_hit_latency = 2
106 self.sequencer.dcache_hit_latency = 2
107 self.sequencer.version = self.seqCount()
108 self.sequencer.icache = self.L1Icache
109 self.sequencer.dcache = self.L1D0cache
110 self.sequencer.ruby_system = ruby_system
111 self.sequencer.coreid = 0
112 self.sequencer.is_cpu_sequencer = True
113
114 self.sequencer1 = RubySequencer()
115 self.sequencer1.version = self.seqCount()
116 self.sequencer1.icache = self.L1Icache
117 self.sequencer1.dcache = self.L1D1cache
118 self.sequencer1.icache_hit_latency = 2
119 self.sequencer1.dcache_hit_latency = 2
120 self.sequencer1.ruby_system = ruby_system
121 self.sequencer1.coreid = 1
122 self.sequencer1.is_cpu_sequencer = True
123
124 self.issue_latency = options.cpu_to_dir_latency
125 self.send_evictions = send_evicts(options)
126
127 self.ruby_system = ruby_system
128
129 if options.recycle_latency:
130 self.recycle_latency = options.recycle_latency
131
132class L3Cache(RubyCache):
133 assoc = 8
134 dataArrayBanks = 256
135 tagArrayBanks = 256
136
137 def create(self, options, ruby_system, system):
138 self.size = MemorySize(options.l3_size)
139 self.size.value /= options.num_dirs
140 self.dataArrayBanks /= options.num_dirs
141 self.tagArrayBanks /= options.num_dirs
142 self.dataArrayBanks /= options.num_dirs
143 self.tagArrayBanks /= options.num_dirs
144 self.dataAccessLatency = options.l3_data_latency
145 self.tagAccessLatency = options.l3_tag_latency
146 self.resourceStalls = options.no_resource_stalls
147 self.replacement_policy = PseudoLRUReplacementPolicy()
148
149class L3Cntrl(L3Cache_Controller, CntrlBase):
150 def create(self, options, ruby_system, system):
151 self.version = self.versionCount()
152 self.L3cache = L3Cache()
153 self.L3cache.create(options, ruby_system, system)
154
155 self.l3_response_latency = max(self.L3cache.dataAccessLatency,
156 self.L3cache.tagAccessLatency)
157 self.ruby_system = ruby_system
158
159 if options.recycle_latency:
160 self.recycle_latency = options.recycle_latency
161
162 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
163 req_to_l3, probe_to_l3, resp_to_l3):
164 self.reqToDir = req_to_dir
165 self.respToDir = resp_to_dir
166 self.l3UnblockToDir = l3_unblock_to_dir
167 self.reqToL3 = req_to_l3
168 self.probeToL3 = probe_to_l3
169 self.respToL3 = resp_to_l3
170
171class DirCntrl(Directory_Controller, CntrlBase):
172 def create(self, options, dir_ranges, ruby_system, system):
173 self.version = self.versionCount()
174
175 self.response_latency = 30
176
177 self.addr_ranges = dir_ranges
178 self.directory = RubyDirectoryMemory()
179
180 self.L3CacheMemory = L3Cache()
181 self.L3CacheMemory.create(options, ruby_system, system)
182
183 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency,
184 self.L3CacheMemory.tagAccessLatency)
185
186 self.number_of_TBEs = options.num_tbes
187
188 self.ruby_system = ruby_system
189
190 if options.recycle_latency:
191 self.recycle_latency = options.recycle_latency
192
193 self.CPUonly = True
194
195 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
196 req_to_l3, probe_to_l3, resp_to_l3):
197 self.reqToDir = req_to_dir
198 self.respToDir = resp_to_dir
199 self.l3UnblockToDir = l3_unblock_to_dir
200 self.reqToL3 = req_to_l3
201 self.probeToL3 = probe_to_l3
202 self.respToL3 = resp_to_l3
203
204def define_options(parser):
205 parser.add_option("--num-subcaches", type="int", default=4)
206 parser.add_option("--l3-data-latency", type="int", default=20)
207 parser.add_option("--l3-tag-latency", type="int", default=15)
208 parser.add_option("--cpu-to-dir-latency", type="int", default=15)
209 parser.add_option("--no-resource-stalls", action="store_false",
210 default=True)
211 parser.add_option("--num-tbes", type="int", default=256)
212 parser.add_option("--l2-latency", type="int", default=50) # load to use
213
214def create_system(options, full_system, system, dma_devices, bootmem,
215 ruby_system):
216 if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base':
217 panic("This script requires the MOESI_AMD_Base protocol.")
218
219 cpu_sequencers = []
220
221 #
222 # The ruby network creation expects the list of nodes in the system to
223 # be consistent with the NetDest list. Therefore the l1 controller
224 # nodes must be listed before the directory nodes and directory nodes
225 # before dma nodes, etc.
226 #
227 l1_cntrl_nodes = []
228 l3_cntrl_nodes = []
229 dir_cntrl_nodes = []
230
231 control_count = 0
232
233 #
234 # Must create the individual controllers before the network to ensure
235 # the controller constructors are called before the network constructor
236 #
237
238 # This is the base crossbar that connects the L3s, Dirs, and cpu
239 # Cluster
240 mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
241
242 if options.numa_high_bit:
243 numa_bit = options.numa_high_bit
244 else:
245 # if the numa_bit is not specified, set the directory bits as the
246 # lowest bits above the block offset bits, and the numa_bit as the
247 # highest of those directory bits
248 dir_bits = int(math.log(options.num_dirs, 2))
249 block_size_bits = int(math.log(options.cacheline_size, 2))
250 numa_bit = block_size_bits + dir_bits - 1
251
252 for i in range(options.num_dirs):
253 dir_ranges = []
254 for r in system.mem_ranges:
255 addr_range = m5.objects.AddrRange(r.start, size = r.size(),
256 intlvHighBit = numa_bit,
257 intlvBits = dir_bits,
258 intlvMatch = i)
259 dir_ranges.append(addr_range)
260
261
262 dir_cntrl = DirCntrl(TCC_select_num_bits = 0)
263 dir_cntrl.create(options, dir_ranges, ruby_system, system)
264
265 # Connect the Directory controller to the ruby network
266 dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
267 dir_cntrl.requestFromCores.slave = ruby_system.network.master
268
269 dir_cntrl.responseFromCores = MessageBuffer()
270 dir_cntrl.responseFromCores.slave = ruby_system.network.master
271
272 dir_cntrl.unblockFromCores = MessageBuffer()
273 dir_cntrl.unblockFromCores.slave = ruby_system.network.master
274
275 dir_cntrl.probeToCore = MessageBuffer()
276 dir_cntrl.probeToCore.master = ruby_system.network.slave
277
278 dir_cntrl.responseToCore = MessageBuffer()
279 dir_cntrl.responseToCore.master = ruby_system.network.slave
280
281 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
282 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
283 dir_cntrl.responseFromMemory = MessageBuffer()
284
285 exec("system.dir_cntrl%d = dir_cntrl" % i)
286 dir_cntrl_nodes.append(dir_cntrl)
287
288 mainCluster.add(dir_cntrl)
289
290 # Technically this config can support an odd number of cpus, but the top
291 # level config files, such as the ruby_random_tester, will get confused if
292 # the number of cpus does not equal the number of sequencers. Thus make
293 # sure that an even number of cpus is specified.
294 assert((options.num_cpus % 2) == 0)
295
296 # For an odd number of CPUs, still create the right number of controllers
297 cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
298 for i in range((options.num_cpus + 1) // 2):
299
300 cp_cntrl = CPCntrl()
301 cp_cntrl.create(options, ruby_system, system)
302
303 exec("system.cp_cntrl%d = cp_cntrl" % i)
304 #
305 # Add controllers and sequencers to the appropriate lists
306 #
307 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
308
309 # Connect the CP controllers and the network
310 cp_cntrl.requestFromCore = MessageBuffer()
311 cp_cntrl.requestFromCore.master = ruby_system.network.slave
312
313 cp_cntrl.responseFromCore = MessageBuffer()
314 cp_cntrl.responseFromCore.master = ruby_system.network.slave
315
316 cp_cntrl.unblockFromCore = MessageBuffer()
317 cp_cntrl.unblockFromCore.master = ruby_system.network.slave
318
319 cp_cntrl.probeToCore = MessageBuffer()
320 cp_cntrl.probeToCore.slave = ruby_system.network.master
321
322 cp_cntrl.responseToCore = MessageBuffer()
323 cp_cntrl.responseToCore.slave = ruby_system.network.master
324
325 cp_cntrl.mandatoryQueue = MessageBuffer()
326 cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
327
328 cpuCluster.add(cp_cntrl)
329
330 # Register CPUs and caches for each CorePair and directory (SE mode only)
331 if not full_system:
332 FileSystemConfig.config_filesystem(options)
333 for i in xrange((options.num_cpus + 1) // 2):
334 FileSystemConfig.register_cpu(physical_package_id = 0,
335 core_siblings =
336 xrange(options.num_cpus),
337 core_id = i*2,
338 thread_siblings = [])
339
340 FileSystemConfig.register_cpu(physical_package_id = 0,
341 core_siblings =
342 xrange(options.num_cpus),
343 core_id = i*2+1,
344 thread_siblings = [])
345
346 FileSystemConfig.register_cache(level = 0,
347 idu_type = 'Instruction',
348 size = options.l1i_size,
349 line_size = options.cacheline_size,
350 assoc = options.l1i_assoc,
351 cpus = [i*2, i*2+1])
352
353 FileSystemConfig.register_cache(level = 0,
354 idu_type = 'Data',
355 size = options.l1d_size,
356 line_size = options.cacheline_size,
357 assoc = options.l1d_assoc,
358 cpus = [i*2])
359
360 FileSystemConfig.register_cache(level = 0,
361 idu_type = 'Data',
362 size = options.l1d_size,
363 line_size = options.cacheline_size,
364 assoc = options.l1d_assoc,
365 cpus = [i*2+1])
366
367 FileSystemConfig.register_cache(level = 1,
368 idu_type = 'Unified',
369 size = options.l2_size,
370 line_size = options.cacheline_size,
371 assoc = options.l2_assoc,
372 cpus = [i*2, i*2+1])
373
374 for i in range(options.num_dirs):
375 FileSystemConfig.register_cache(level = 2,
376 idu_type = 'Unified',
377 size = options.l3_size,
378 line_size = options.cacheline_size,
379 assoc = options.l3_assoc,
380 cpus = [n for n in
381 xrange(options.num_cpus)])
382
383 # Assuming no DMA devices
384 assert(len(dma_devices) == 0)
385
386 # Add cpu/gpu clusters to main cluster
387 mainCluster.add(cpuCluster)
388
389 ruby_system.network.number_of_virtual_networks = 10
390
391 return (cpu_sequencers, dir_cntrl_nodes, mainCluster)
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