1# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#
9# 1. Redistributions of source code must retain the above copyright notice,
10# this list of conditions and the following disclaimer.
11#
12# 2. Redistributions in binary form must reproduce the above copyright notice,
13# this list of conditions and the following disclaimer in the documentation
14# and/or other materials provided with the distribution.
15#
16# 3. Neither the name of the copyright holder nor the names of its
17# contributors may be used to endorse or promote products derived from this
18# software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30# POSSIBILITY OF SUCH DAMAGE.
31#
32# Authors: Lisa Hsu
33
34import math
35import m5
36from m5.objects import *
37from m5.defines import buildEnv
38from m5.util import addToPath
39from Ruby import create_topology
40from Ruby import send_evicts
41
42addToPath('../')
43
44from topologies.Cluster import Cluster
45from topologies.Crossbar import Crossbar
46
47class CntrlBase:
48 _seqs = 0
49 @classmethod
50 def seqCount(cls):
51 # Use SeqCount not class since we need global count
52 CntrlBase._seqs += 1
53 return CntrlBase._seqs - 1
54
55 _cntrls = 0
56 @classmethod
57 def cntrlCount(cls):
58 # Use CntlCount not class since we need global count
59 CntrlBase._cntrls += 1
60 return CntrlBase._cntrls - 1
61
62 _version = 0
63 @classmethod
64 def versionCount(cls):
65 cls._version += 1 # Use count for this particular type
66 return cls._version - 1
67
68class L1DCache(RubyCache):
69 resourceStalls = False
70 def create(self, options):
71 self.size = MemorySize(options.l1d_size)
72 self.assoc = options.l1d_assoc
73 self.replacement_policy = PseudoLRUReplacementPolicy()
74
75class L1ICache(RubyCache):
76 resourceStalls = False
77 def create(self, options):
78 self.size = MemorySize(options.l1i_size)
79 self.assoc = options.l1i_assoc
80 self.replacement_policy = PseudoLRUReplacementPolicy()
81
82class L2Cache(RubyCache):
83 resourceStalls = False
84 def create(self, options):
85 self.size = MemorySize(options.l2_size)
86 self.assoc = options.l2_assoc
87 self.replacement_policy = PseudoLRUReplacementPolicy()
88
89class CPCntrl(CorePair_Controller, CntrlBase):
90
91 def create(self, options, ruby_system, system):
92 self.version = self.versionCount()
93
94 self.L1Icache = L1ICache()
95 self.L1Icache.create(options)
96 self.L1D0cache = L1DCache()
97 self.L1D0cache.create(options)
98 self.L1D1cache = L1DCache()
99 self.L1D1cache.create(options)
100 self.L2cache = L2Cache()
101 self.L2cache.create(options)
102
103 self.sequencer = RubySequencer()
104 self.sequencer.icache_hit_latency = 2
105 self.sequencer.dcache_hit_latency = 2
106 self.sequencer.version = self.seqCount()
107 self.sequencer.icache = self.L1Icache
108 self.sequencer.dcache = self.L1D0cache
109 self.sequencer.ruby_system = ruby_system
110 self.sequencer.coreid = 0
111 self.sequencer.is_cpu_sequencer = True
112
113 self.sequencer1 = RubySequencer()
114 self.sequencer1.version = self.seqCount()
115 self.sequencer1.icache = self.L1Icache
116 self.sequencer1.dcache = self.L1D1cache
117 self.sequencer1.icache_hit_latency = 2
118 self.sequencer1.dcache_hit_latency = 2
119 self.sequencer1.ruby_system = ruby_system
120 self.sequencer1.coreid = 1
121 self.sequencer1.is_cpu_sequencer = True
122
123 self.issue_latency = options.cpu_to_dir_latency
124 self.send_evictions = send_evicts(options)
125
126 self.ruby_system = ruby_system
127
128 if options.recycle_latency:
129 self.recycle_latency = options.recycle_latency
130
131class L3Cache(RubyCache):
132 assoc = 8
133 dataArrayBanks = 256
134 tagArrayBanks = 256
135
136 def create(self, options, ruby_system, system):
137 self.size = MemorySize(options.l3_size)
138 self.size.value /= options.num_dirs
139 self.dataArrayBanks /= options.num_dirs
140 self.tagArrayBanks /= options.num_dirs
141 self.dataArrayBanks /= options.num_dirs
142 self.tagArrayBanks /= options.num_dirs
143 self.dataAccessLatency = options.l3_data_latency
144 self.tagAccessLatency = options.l3_tag_latency
145 self.resourceStalls = options.no_resource_stalls
146 self.replacement_policy = PseudoLRUReplacementPolicy()
147
148class L3Cntrl(L3Cache_Controller, CntrlBase):
149 def create(self, options, ruby_system, system):
150 self.version = self.versionCount()
151 self.L3cache = L3Cache()
152 self.L3cache.create(options, ruby_system, system)
153
154 self.l3_response_latency = max(self.L3cache.dataAccessLatency,
155 self.L3cache.tagAccessLatency)
156 self.ruby_system = ruby_system
157
158 if options.recycle_latency:
159 self.recycle_latency = options.recycle_latency
160
161 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
162 req_to_l3, probe_to_l3, resp_to_l3):
163 self.reqToDir = req_to_dir
164 self.respToDir = resp_to_dir
165 self.l3UnblockToDir = l3_unblock_to_dir
166 self.reqToL3 = req_to_l3
167 self.probeToL3 = probe_to_l3
168 self.respToL3 = resp_to_l3
169
170class DirCntrl(Directory_Controller, CntrlBase):
171 def create(self, options, dir_ranges, ruby_system, system):
172 self.version = self.versionCount()
173
174 self.response_latency = 30
175
176 self.addr_ranges = dir_ranges
177 self.directory = RubyDirectoryMemory()
178
179 self.L3CacheMemory = L3Cache()
180 self.L3CacheMemory.create(options, ruby_system, system)
181
182 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency,
183 self.L3CacheMemory.tagAccessLatency)
184
185 self.number_of_TBEs = options.num_tbes
186
187 self.ruby_system = ruby_system
188
189 if options.recycle_latency:
190 self.recycle_latency = options.recycle_latency
191
192 self.CPUonly = True
193
194 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
195 req_to_l3, probe_to_l3, resp_to_l3):
196 self.reqToDir = req_to_dir
197 self.respToDir = resp_to_dir
198 self.l3UnblockToDir = l3_unblock_to_dir
199 self.reqToL3 = req_to_l3
200 self.probeToL3 = probe_to_l3
201 self.respToL3 = resp_to_l3
202
203def define_options(parser):
204 parser.add_option("--num-subcaches", type="int", default=4)
205 parser.add_option("--l3-data-latency", type="int", default=20)
206 parser.add_option("--l3-tag-latency", type="int", default=15)
207 parser.add_option("--cpu-to-dir-latency", type="int", default=15)
208 parser.add_option("--no-resource-stalls", action="store_false",
209 default=True)
210 parser.add_option("--num-tbes", type="int", default=256)
211 parser.add_option("--l2-latency", type="int", default=50) # load to use
212
213def create_system(options, full_system, system, dma_devices, bootmem,
214 ruby_system):
215 if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base':
216 panic("This script requires the MOESI_AMD_Base protocol.")
217
218 cpu_sequencers = []
219
220 #
221 # The ruby network creation expects the list of nodes in the system to
222 # be consistent with the NetDest list. Therefore the l1 controller
223 # nodes must be listed before the directory nodes and directory nodes
224 # before dma nodes, etc.
225 #
226 l1_cntrl_nodes = []
227 l3_cntrl_nodes = []
228 dir_cntrl_nodes = []
229
230 control_count = 0
231
232 #
233 # Must create the individual controllers before the network to ensure
234 # the controller constructors are called before the network constructor
235 #
236
237 # This is the base crossbar that connects the L3s, Dirs, and cpu
238 # Cluster
239 mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
240
241 if options.numa_high_bit:
242 numa_bit = options.numa_high_bit
243 else:
244 # if the numa_bit is not specified, set the directory bits as the
245 # lowest bits above the block offset bits, and the numa_bit as the
246 # highest of those directory bits
247 dir_bits = int(math.log(options.num_dirs, 2))
248 block_size_bits = int(math.log(options.cacheline_size, 2))
249 numa_bit = block_size_bits + dir_bits - 1
250
| 1# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#
9# 1. Redistributions of source code must retain the above copyright notice,
10# this list of conditions and the following disclaimer.
11#
12# 2. Redistributions in binary form must reproduce the above copyright notice,
13# this list of conditions and the following disclaimer in the documentation
14# and/or other materials provided with the distribution.
15#
16# 3. Neither the name of the copyright holder nor the names of its
17# contributors may be used to endorse or promote products derived from this
18# software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30# POSSIBILITY OF SUCH DAMAGE.
31#
32# Authors: Lisa Hsu
33
34import math
35import m5
36from m5.objects import *
37from m5.defines import buildEnv
38from m5.util import addToPath
39from Ruby import create_topology
40from Ruby import send_evicts
41
42addToPath('../')
43
44from topologies.Cluster import Cluster
45from topologies.Crossbar import Crossbar
46
47class CntrlBase:
48 _seqs = 0
49 @classmethod
50 def seqCount(cls):
51 # Use SeqCount not class since we need global count
52 CntrlBase._seqs += 1
53 return CntrlBase._seqs - 1
54
55 _cntrls = 0
56 @classmethod
57 def cntrlCount(cls):
58 # Use CntlCount not class since we need global count
59 CntrlBase._cntrls += 1
60 return CntrlBase._cntrls - 1
61
62 _version = 0
63 @classmethod
64 def versionCount(cls):
65 cls._version += 1 # Use count for this particular type
66 return cls._version - 1
67
68class L1DCache(RubyCache):
69 resourceStalls = False
70 def create(self, options):
71 self.size = MemorySize(options.l1d_size)
72 self.assoc = options.l1d_assoc
73 self.replacement_policy = PseudoLRUReplacementPolicy()
74
75class L1ICache(RubyCache):
76 resourceStalls = False
77 def create(self, options):
78 self.size = MemorySize(options.l1i_size)
79 self.assoc = options.l1i_assoc
80 self.replacement_policy = PseudoLRUReplacementPolicy()
81
82class L2Cache(RubyCache):
83 resourceStalls = False
84 def create(self, options):
85 self.size = MemorySize(options.l2_size)
86 self.assoc = options.l2_assoc
87 self.replacement_policy = PseudoLRUReplacementPolicy()
88
89class CPCntrl(CorePair_Controller, CntrlBase):
90
91 def create(self, options, ruby_system, system):
92 self.version = self.versionCount()
93
94 self.L1Icache = L1ICache()
95 self.L1Icache.create(options)
96 self.L1D0cache = L1DCache()
97 self.L1D0cache.create(options)
98 self.L1D1cache = L1DCache()
99 self.L1D1cache.create(options)
100 self.L2cache = L2Cache()
101 self.L2cache.create(options)
102
103 self.sequencer = RubySequencer()
104 self.sequencer.icache_hit_latency = 2
105 self.sequencer.dcache_hit_latency = 2
106 self.sequencer.version = self.seqCount()
107 self.sequencer.icache = self.L1Icache
108 self.sequencer.dcache = self.L1D0cache
109 self.sequencer.ruby_system = ruby_system
110 self.sequencer.coreid = 0
111 self.sequencer.is_cpu_sequencer = True
112
113 self.sequencer1 = RubySequencer()
114 self.sequencer1.version = self.seqCount()
115 self.sequencer1.icache = self.L1Icache
116 self.sequencer1.dcache = self.L1D1cache
117 self.sequencer1.icache_hit_latency = 2
118 self.sequencer1.dcache_hit_latency = 2
119 self.sequencer1.ruby_system = ruby_system
120 self.sequencer1.coreid = 1
121 self.sequencer1.is_cpu_sequencer = True
122
123 self.issue_latency = options.cpu_to_dir_latency
124 self.send_evictions = send_evicts(options)
125
126 self.ruby_system = ruby_system
127
128 if options.recycle_latency:
129 self.recycle_latency = options.recycle_latency
130
131class L3Cache(RubyCache):
132 assoc = 8
133 dataArrayBanks = 256
134 tagArrayBanks = 256
135
136 def create(self, options, ruby_system, system):
137 self.size = MemorySize(options.l3_size)
138 self.size.value /= options.num_dirs
139 self.dataArrayBanks /= options.num_dirs
140 self.tagArrayBanks /= options.num_dirs
141 self.dataArrayBanks /= options.num_dirs
142 self.tagArrayBanks /= options.num_dirs
143 self.dataAccessLatency = options.l3_data_latency
144 self.tagAccessLatency = options.l3_tag_latency
145 self.resourceStalls = options.no_resource_stalls
146 self.replacement_policy = PseudoLRUReplacementPolicy()
147
148class L3Cntrl(L3Cache_Controller, CntrlBase):
149 def create(self, options, ruby_system, system):
150 self.version = self.versionCount()
151 self.L3cache = L3Cache()
152 self.L3cache.create(options, ruby_system, system)
153
154 self.l3_response_latency = max(self.L3cache.dataAccessLatency,
155 self.L3cache.tagAccessLatency)
156 self.ruby_system = ruby_system
157
158 if options.recycle_latency:
159 self.recycle_latency = options.recycle_latency
160
161 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
162 req_to_l3, probe_to_l3, resp_to_l3):
163 self.reqToDir = req_to_dir
164 self.respToDir = resp_to_dir
165 self.l3UnblockToDir = l3_unblock_to_dir
166 self.reqToL3 = req_to_l3
167 self.probeToL3 = probe_to_l3
168 self.respToL3 = resp_to_l3
169
170class DirCntrl(Directory_Controller, CntrlBase):
171 def create(self, options, dir_ranges, ruby_system, system):
172 self.version = self.versionCount()
173
174 self.response_latency = 30
175
176 self.addr_ranges = dir_ranges
177 self.directory = RubyDirectoryMemory()
178
179 self.L3CacheMemory = L3Cache()
180 self.L3CacheMemory.create(options, ruby_system, system)
181
182 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency,
183 self.L3CacheMemory.tagAccessLatency)
184
185 self.number_of_TBEs = options.num_tbes
186
187 self.ruby_system = ruby_system
188
189 if options.recycle_latency:
190 self.recycle_latency = options.recycle_latency
191
192 self.CPUonly = True
193
194 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
195 req_to_l3, probe_to_l3, resp_to_l3):
196 self.reqToDir = req_to_dir
197 self.respToDir = resp_to_dir
198 self.l3UnblockToDir = l3_unblock_to_dir
199 self.reqToL3 = req_to_l3
200 self.probeToL3 = probe_to_l3
201 self.respToL3 = resp_to_l3
202
203def define_options(parser):
204 parser.add_option("--num-subcaches", type="int", default=4)
205 parser.add_option("--l3-data-latency", type="int", default=20)
206 parser.add_option("--l3-tag-latency", type="int", default=15)
207 parser.add_option("--cpu-to-dir-latency", type="int", default=15)
208 parser.add_option("--no-resource-stalls", action="store_false",
209 default=True)
210 parser.add_option("--num-tbes", type="int", default=256)
211 parser.add_option("--l2-latency", type="int", default=50) # load to use
212
213def create_system(options, full_system, system, dma_devices, bootmem,
214 ruby_system):
215 if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base':
216 panic("This script requires the MOESI_AMD_Base protocol.")
217
218 cpu_sequencers = []
219
220 #
221 # The ruby network creation expects the list of nodes in the system to
222 # be consistent with the NetDest list. Therefore the l1 controller
223 # nodes must be listed before the directory nodes and directory nodes
224 # before dma nodes, etc.
225 #
226 l1_cntrl_nodes = []
227 l3_cntrl_nodes = []
228 dir_cntrl_nodes = []
229
230 control_count = 0
231
232 #
233 # Must create the individual controllers before the network to ensure
234 # the controller constructors are called before the network constructor
235 #
236
237 # This is the base crossbar that connects the L3s, Dirs, and cpu
238 # Cluster
239 mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
240
241 if options.numa_high_bit:
242 numa_bit = options.numa_high_bit
243 else:
244 # if the numa_bit is not specified, set the directory bits as the
245 # lowest bits above the block offset bits, and the numa_bit as the
246 # highest of those directory bits
247 dir_bits = int(math.log(options.num_dirs, 2))
248 block_size_bits = int(math.log(options.cacheline_size, 2))
249 numa_bit = block_size_bits + dir_bits - 1
250
|