MI_example.py (9841:69c158420c51) | MI_example.py (10006:8fa94dcfd545) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59 dma_cntrl_nodes = [] 60 61 # 62 # Must create the individual controllers before the network to ensure the 63 # controller constructors are called before the network constructor 64 # 65 block_size_bits = int(math.log(options.cacheline_size, 2)) 66 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59 dma_cntrl_nodes = [] 60 61 # 62 # Must create the individual controllers before the network to ensure the 63 # controller constructors are called before the network constructor 64 # 65 block_size_bits = int(math.log(options.cacheline_size, 2)) 66 |
67 cntrl_count = 0 68 | |
69 for i in xrange(options.num_cpus): 70 # 71 # First create the Ruby objects associated with this cpu 72 # Only one cache exists for this protocol, so by default use the L1D 73 # config parameters. 74 # 75 cache = Cache(size = options.l1d_size, 76 assoc = options.l1d_assoc, 77 start_index_bit = block_size_bits) 78 79 # 80 # Only one unified L1 cache exists. Can cache instructions and data. 81 # 82 l1_cntrl = L1Cache_Controller(version = i, | 67 for i in xrange(options.num_cpus): 68 # 69 # First create the Ruby objects associated with this cpu 70 # Only one cache exists for this protocol, so by default use the L1D 71 # config parameters. 72 # 73 cache = Cache(size = options.l1d_size, 74 assoc = options.l1d_assoc, 75 start_index_bit = block_size_bits) 76 77 # 78 # Only one unified L1 cache exists. Can cache instructions and data. 79 # 80 l1_cntrl = L1Cache_Controller(version = i, |
83 cntrl_id = cntrl_count, | |
84 cacheMemory = cache, 85 send_evictions = ( 86 options.cpu_type == "detailed"), 87 transitions_per_cycle = options.ports, 88 ruby_system = ruby_system) 89 90 cpu_seq = RubySequencer(version = i, 91 icache = cache, --- 7 unchanged lines hidden (view full) --- 99 100 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 101 # 102 # Add controllers and sequencers to the appropriate lists 103 # 104 cpu_sequencers.append(cpu_seq) 105 l1_cntrl_nodes.append(l1_cntrl) 106 | 81 cacheMemory = cache, 82 send_evictions = ( 83 options.cpu_type == "detailed"), 84 transitions_per_cycle = options.ports, 85 ruby_system = ruby_system) 86 87 cpu_seq = RubySequencer(version = i, 88 icache = cache, --- 7 unchanged lines hidden (view full) --- 96 97 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 98 # 99 # Add controllers and sequencers to the appropriate lists 100 # 101 cpu_sequencers.append(cpu_seq) 102 l1_cntrl_nodes.append(l1_cntrl) 103 |
107 cntrl_count += 1 108 | |
109 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 110 assert(phys_mem_size % options.num_dirs == 0) 111 mem_module_size = phys_mem_size / options.num_dirs 112 113 # Run each of the ruby memory controllers at a ratio of the frequency of 114 # the ruby system. 115 # clk_divider value is a fix to pass regression. 116 ruby_system.memctrl_clk_domain = DerivedClockDomain( --- 9 unchanged lines hidden (view full) --- 126 clk_domain = ruby_system.memctrl_clk_domain, 127 version = i, 128 ruby_system = ruby_system) 129 130 dir_size = MemorySize('0B') 131 dir_size.value = mem_module_size 132 133 dir_cntrl = Directory_Controller(version = i, | 104 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 105 assert(phys_mem_size % options.num_dirs == 0) 106 mem_module_size = phys_mem_size / options.num_dirs 107 108 # Run each of the ruby memory controllers at a ratio of the frequency of 109 # the ruby system. 110 # clk_divider value is a fix to pass regression. 111 ruby_system.memctrl_clk_domain = DerivedClockDomain( --- 9 unchanged lines hidden (view full) --- 121 clk_domain = ruby_system.memctrl_clk_domain, 122 version = i, 123 ruby_system = ruby_system) 124 125 dir_size = MemorySize('0B') 126 dir_size.value = mem_module_size 127 128 dir_cntrl = Directory_Controller(version = i, |
134 cntrl_id = cntrl_count, | |
135 directory = \ 136 RubyDirectoryMemory( \ 137 version = i, 138 size = dir_size, 139 use_map = options.use_map, 140 map_levels = \ 141 options.map_levels), 142 memBuffer = mem_cntrl, 143 transitions_per_cycle = options.ports, 144 ruby_system = ruby_system) 145 146 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 147 dir_cntrl_nodes.append(dir_cntrl) 148 | 129 directory = \ 130 RubyDirectoryMemory( \ 131 version = i, 132 size = dir_size, 133 use_map = options.use_map, 134 map_levels = \ 135 options.map_levels), 136 memBuffer = mem_cntrl, 137 transitions_per_cycle = options.ports, 138 ruby_system = ruby_system) 139 140 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 141 dir_cntrl_nodes.append(dir_cntrl) 142 |
149 cntrl_count += 1 150 | |
151 for i, dma_port in enumerate(dma_ports): 152 # 153 # Create the Ruby objects associated with the dma controller 154 # 155 dma_seq = DMASequencer(version = i, 156 ruby_system = ruby_system) 157 158 dma_cntrl = DMA_Controller(version = i, | 143 for i, dma_port in enumerate(dma_ports): 144 # 145 # Create the Ruby objects associated with the dma controller 146 # 147 dma_seq = DMASequencer(version = i, 148 ruby_system = ruby_system) 149 150 dma_cntrl = DMA_Controller(version = i, |
159 cntrl_id = cntrl_count, | |
160 dma_sequencer = dma_seq, 161 transitions_per_cycle = options.ports, 162 ruby_system = ruby_system) 163 164 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 165 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 166 dma_cntrl_nodes.append(dma_cntrl) | 151 dma_sequencer = dma_seq, 152 transitions_per_cycle = options.ports, 153 ruby_system = ruby_system) 154 155 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 156 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 157 dma_cntrl_nodes.append(dma_cntrl) |
167 cntrl_count += 1 | |
168 169 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 170 171 topology = create_topology(all_cntrls, options) 172 173 return (cpu_sequencers, dir_cntrl_nodes, topology) | 158 159 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 160 161 topology = create_topology(all_cntrls, options) 162 163 return (cpu_sequencers, dir_cntrl_nodes, topology) |