MI_example.py (9826:014ff1fbff6d) MI_example.py (9841:69c158420c51)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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79 #
80 # Only one unified L1 cache exists. Can cache instructions and data.
81 #
82 l1_cntrl = L1Cache_Controller(version = i,
83 cntrl_id = cntrl_count,
84 cacheMemory = cache,
85 send_evictions = (
86 options.cpu_type == "detailed"),
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 70 unchanged lines hidden (view full) ---

79 #
80 # Only one unified L1 cache exists. Can cache instructions and data.
81 #
82 l1_cntrl = L1Cache_Controller(version = i,
83 cntrl_id = cntrl_count,
84 cacheMemory = cache,
85 send_evictions = (
86 options.cpu_type == "detailed"),
87 transitions_per_cycle = options.ports,
87 ruby_system = ruby_system)
88
89 cpu_seq = RubySequencer(version = i,
90 icache = cache,
91 dcache = cache,
92 ruby_system = ruby_system)
93
94 l1_cntrl.sequencer = cpu_seq

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134 directory = \
135 RubyDirectoryMemory( \
136 version = i,
137 size = dir_size,
138 use_map = options.use_map,
139 map_levels = \
140 options.map_levels),
141 memBuffer = mem_cntrl,
88 ruby_system = ruby_system)
89
90 cpu_seq = RubySequencer(version = i,
91 icache = cache,
92 dcache = cache,
93 ruby_system = ruby_system)
94
95 l1_cntrl.sequencer = cpu_seq

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135 directory = \
136 RubyDirectoryMemory( \
137 version = i,
138 size = dir_size,
139 use_map = options.use_map,
140 map_levels = \
141 options.map_levels),
142 memBuffer = mem_cntrl,
143 transitions_per_cycle = options.ports,
142 ruby_system = ruby_system)
143
144 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
145 dir_cntrl_nodes.append(dir_cntrl)
146
147 cntrl_count += 1
148
149 for i, dma_port in enumerate(dma_ports):
150 #
151 # Create the Ruby objects associated with the dma controller
152 #
153 dma_seq = DMASequencer(version = i,
154 ruby_system = ruby_system)
155
156 dma_cntrl = DMA_Controller(version = i,
157 cntrl_id = cntrl_count,
158 dma_sequencer = dma_seq,
144 ruby_system = ruby_system)
145
146 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
147 dir_cntrl_nodes.append(dir_cntrl)
148
149 cntrl_count += 1
150
151 for i, dma_port in enumerate(dma_ports):
152 #
153 # Create the Ruby objects associated with the dma controller
154 #
155 dma_seq = DMASequencer(version = i,
156 ruby_system = ruby_system)
157
158 dma_cntrl = DMA_Controller(version = i,
159 cntrl_id = cntrl_count,
160 dma_sequencer = dma_seq,
161 transitions_per_cycle = options.ports,
159 ruby_system = ruby_system)
160
161 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
162 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
163 dma_cntrl_nodes.append(dma_cntrl)
164 cntrl_count += 1
165
166 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
167
168 topology = create_topology(all_cntrls, options)
169
170 return (cpu_sequencers, dir_cntrl_nodes, topology)
162 ruby_system = ruby_system)
163
164 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
165 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
166 dma_cntrl_nodes.append(dma_cntrl)
167 cntrl_count += 1
168
169 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
170
171 topology = create_topology(all_cntrls, options)
172
173 return (cpu_sequencers, dir_cntrl_nodes, topology)