MI_example.py (9793:6e6cefc1db1f) MI_example.py (9798:52679402e09c)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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102 #
103 cpu_sequencers.append(cpu_seq)
104 l1_cntrl_nodes.append(l1_cntrl)
105
106 cntrl_count += 1
107
108 phys_mem_size = sum(map(lambda mem: mem.range.size(),
109 system.memories.unproxy(system)))
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 93 unchanged lines hidden (view full) ---

102 #
103 cpu_sequencers.append(cpu_seq)
104 l1_cntrl_nodes.append(l1_cntrl)
105
106 cntrl_count += 1
107
108 phys_mem_size = sum(map(lambda mem: mem.range.size(),
109 system.memories.unproxy(system)))
110 assert(phys_mem_size % options.num_dirs == 0)
110 mem_module_size = phys_mem_size / options.num_dirs
111
112 # Run each of the ruby memory controllers at a ratio of the frequency of
113 # the ruby system.
114 # clk_divider value is a fix to pass regression.
115 ruby_system.memctrl_clk_domain = DerivedClockDomain(
116 clk_domain=ruby_system.clk_domain,
117 clk_divider=3)

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111 mem_module_size = phys_mem_size / options.num_dirs
112
113 # Run each of the ruby memory controllers at a ratio of the frequency of
114 # the ruby system.
115 # clk_divider value is a fix to pass regression.
116 ruby_system.memctrl_clk_domain = DerivedClockDomain(
117 clk_domain=ruby_system.clk_domain,
118 clk_divider=3)

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