MI_example.py (9232:3bb99fab80d4) MI_example.py (9468:721718c62859)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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91 dcache = cache,
92 ruby_system = ruby_system)
93
94 l1_cntrl.sequencer = cpu_seq
95
96 if piobus != None:
97 cpu_seq.pio_port = piobus.slave
98
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 82 unchanged lines hidden (view full) ---

91 dcache = cache,
92 ruby_system = ruby_system)
93
94 l1_cntrl.sequencer = cpu_seq
95
96 if piobus != None:
97 cpu_seq.pio_port = piobus.slave
98
99 exec("system.l1_cntrl%d = l1_cntrl" % i)
99 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
100 #
101 # Add controllers and sequencers to the appropriate lists
102 #
103 cpu_sequencers.append(cpu_seq)
104 l1_cntrl_nodes.append(l1_cntrl)
105
106 cntrl_count += 1
107

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127 version = i,
128 size = dir_size,
129 use_map = options.use_map,
130 map_levels = \
131 options.map_levels),
132 memBuffer = mem_cntrl,
133 ruby_system = ruby_system)
134
100 #
101 # Add controllers and sequencers to the appropriate lists
102 #
103 cpu_sequencers.append(cpu_seq)
104 l1_cntrl_nodes.append(l1_cntrl)
105
106 cntrl_count += 1
107

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127 version = i,
128 size = dir_size,
129 use_map = options.use_map,
130 map_levels = \
131 options.map_levels),
132 memBuffer = mem_cntrl,
133 ruby_system = ruby_system)
134
135 exec("system.dir_cntrl%d = dir_cntrl" % i)
135 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
136 dir_cntrl_nodes.append(dir_cntrl)
137
138 cntrl_count += 1
139
140 for i, dma_port in enumerate(dma_ports):
141 #
142 # Create the Ruby objects associated with the dma controller
143 #
144 dma_seq = DMASequencer(version = i,
145 ruby_system = ruby_system)
146
147 dma_cntrl = DMA_Controller(version = i,
148 cntrl_id = cntrl_count,
149 dma_sequencer = dma_seq,
150 ruby_system = ruby_system)
151
136 dir_cntrl_nodes.append(dir_cntrl)
137
138 cntrl_count += 1
139
140 for i, dma_port in enumerate(dma_ports):
141 #
142 # Create the Ruby objects associated with the dma controller
143 #
144 dma_seq = DMASequencer(version = i,
145 ruby_system = ruby_system)
146
147 dma_cntrl = DMA_Controller(version = i,
148 cntrl_id = cntrl_count,
149 dma_sequencer = dma_seq,
150 ruby_system = ruby_system)
151
152 exec("system.dma_cntrl%d = dma_cntrl" % i)
153 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
152 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
153 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
154 dma_cntrl_nodes.append(dma_cntrl)
155 cntrl_count += 1
156
157 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
158
159 topology = create_topology(all_cntrls, options)
160
161 return (cpu_sequencers, dir_cntrl_nodes, topology)
154 dma_cntrl_nodes.append(dma_cntrl)
155 cntrl_count += 1
156
157 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
158
159 topology = create_topology(all_cntrls, options)
160
161 return (cpu_sequencers, dir_cntrl_nodes, topology)