MI_example.py (8931:7a1dfb191e3f) | MI_example.py (9100:3caf131d7a95) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv |
34from Ruby import create_topology |
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34 35# 36# Note: the cache latency is only used by the sequencer on fast path hits 37# 38class Cache(RubyCache): 39 latency = 3 40 41def define_options(parser): --- 108 unchanged lines hidden (view full) --- 150 151 exec("system.dma_cntrl%d = dma_cntrl" % i) 152 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 153 dma_cntrl_nodes.append(dma_cntrl) 154 cntrl_count += 1 155 156 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 157 | 35 36# 37# Note: the cache latency is only used by the sequencer on fast path hits 38# 39class Cache(RubyCache): 40 latency = 3 41 42def define_options(parser): --- 108 unchanged lines hidden (view full) --- 151 152 exec("system.dma_cntrl%d = dma_cntrl" % i) 153 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 154 dma_cntrl_nodes.append(dma_cntrl) 155 cntrl_count += 1 156 157 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 158 |
158 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 159 topology = create_topology(all_cntrls, options) 160 161 return (cpu_sequencers, dir_cntrl_nodes, topology) |