MI_example.py (8923:820111f58fbb) | MI_example.py (8929:4148f9af0b70) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36# Note: the cache latency is only used by the sequencer on fast path hits 37# 38class Cache(RubyCache): 39 latency = 3 40 41def define_options(parser): 42 return 43 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36# Note: the cache latency is only used by the sequencer on fast path hits 37# 38class Cache(RubyCache): 39 latency = 3 40 41def define_options(parser): 42 return 43 |
44def create_system(options, system, piobus, dma_devices, ruby_system): | 44def create_system(options, system, piobus, dma_ports, ruby_system): |
45 46 if buildEnv['PROTOCOL'] != 'MI_example': 47 panic("This script requires the MI_example protocol to be built.") 48 49 cpu_sequencers = [] 50 51 # 52 # The ruby network creation expects the list of nodes in the system to be --- 77 unchanged lines hidden (view full) --- 130 memBuffer = mem_cntrl, 131 ruby_system = ruby_system) 132 133 exec("system.dir_cntrl%d = dir_cntrl" % i) 134 dir_cntrl_nodes.append(dir_cntrl) 135 136 cntrl_count += 1 137 | 45 46 if buildEnv['PROTOCOL'] != 'MI_example': 47 panic("This script requires the MI_example protocol to be built.") 48 49 cpu_sequencers = [] 50 51 # 52 # The ruby network creation expects the list of nodes in the system to be --- 77 unchanged lines hidden (view full) --- 130 memBuffer = mem_cntrl, 131 ruby_system = ruby_system) 132 133 exec("system.dir_cntrl%d = dir_cntrl" % i) 134 dir_cntrl_nodes.append(dir_cntrl) 135 136 cntrl_count += 1 137 |
138 for i, dma_device in enumerate(dma_devices): | 138 for i, dma_port in enumerate(dma_ports): |
139 # 140 # Create the Ruby objects associated with the dma controller 141 # 142 dma_seq = DMASequencer(version = i, 143 ruby_system = ruby_system) 144 145 dma_cntrl = DMA_Controller(version = i, 146 cntrl_id = cntrl_count, 147 dma_sequencer = dma_seq, 148 ruby_system = ruby_system) 149 150 exec("system.dma_cntrl%d = dma_cntrl" % i) | 139 # 140 # Create the Ruby objects associated with the dma controller 141 # 142 dma_seq = DMASequencer(version = i, 143 ruby_system = ruby_system) 144 145 dma_cntrl = DMA_Controller(version = i, 146 cntrl_id = cntrl_count, 147 dma_sequencer = dma_seq, 148 ruby_system = ruby_system) 149 150 exec("system.dma_cntrl%d = dma_cntrl" % i) |
151 if dma_device.type == 'MemTest': 152 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i) 153 else: 154 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i) 155 dma_cntrl.dma_sequencer.slave = dma_device.dma | 151 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) |
156 dma_cntrl_nodes.append(dma_cntrl) | 152 dma_cntrl_nodes.append(dma_cntrl) |
157 | |
158 cntrl_count += 1 159 160 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 161 162 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 153 cntrl_count += 1 154 155 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 156 157 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |