MI_example.py (8475:248a1a32e31b) MI_example.py (8477:4a6c166f61f7)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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136 cntrl_count += 1
137
138 for i, dma_device in enumerate(dma_devices):
139 #
140 # Create the Ruby objects associated with the dma controller
141 #
142 dma_seq = DMASequencer(version = i,
143 physMemPort = system.physmem.port,
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 127 unchanged lines hidden (view full) ---

136 cntrl_count += 1
137
138 for i, dma_device in enumerate(dma_devices):
139 #
140 # Create the Ruby objects associated with the dma controller
141 #
142 dma_seq = DMASequencer(version = i,
143 physMemPort = system.physmem.port,
144 physmem = system.physmem)
144 physmem = system.physmem,
145 ruby_system = ruby_system)
145
146 dma_cntrl = DMA_Controller(version = i,
147 cntrl_id = cntrl_count,
146
147 dma_cntrl = DMA_Controller(version = i,
148 cntrl_id = cntrl_count,
148 dma_sequencer = dma_seq)
149 dma_sequencer = dma_seq,
150 ruby_system = ruby_system)
149
150 exec("system.dma_cntrl%d = dma_cntrl" % i)
151 if dma_device.type == 'MemTest':
152 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
153 else:
154 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
155 dma_cntrl.dma_sequencer.port = dma_device.dma
156 dma_cntrl_nodes.append(dma_cntrl)
157
158 cntrl_count += 1
159
160 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
161
162 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
151
152 exec("system.dma_cntrl%d = dma_cntrl" % i)
153 if dma_device.type == 'MemTest':
154 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
155 else:
156 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
157 dma_cntrl.dma_sequencer.port = dma_device.dma
158 dma_cntrl_nodes.append(dma_cntrl)
159
160 cntrl_count += 1
161
162 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
163
164 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)