MI_example.py (8322:19949c6de823) MI_example.py (8436:5648986156db)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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36# Note: the cache latency is only used by the sequencer on fast path hits
37#
38class Cache(RubyCache):
39 latency = 3
40
41def define_options(parser):
42 return
43
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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36# Note: the cache latency is only used by the sequencer on fast path hits
37#
38class Cache(RubyCache):
39 latency = 3
40
41def define_options(parser):
42 return
43
44def create_system(options, system, piobus, dma_devices):
44def create_system(options, system, piobus, dma_devices, ruby_system):
45
46 if buildEnv['PROTOCOL'] != 'MI_example':
47 panic("This script requires the MI_example protocol to be built.")
48
49 cpu_sequencers = []
50
51 #
52 # The ruby network creation expects the list of nodes in the system to be

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75 assoc = options.l1d_assoc,
76 start_index_bit = block_size_bits)
77
78 #
79 # Only one unified L1 cache exists. Can cache instructions and data.
80 #
81 l1_cntrl = L1Cache_Controller(version = i,
82 cntrl_id = cntrl_count,
45
46 if buildEnv['PROTOCOL'] != 'MI_example':
47 panic("This script requires the MI_example protocol to be built.")
48
49 cpu_sequencers = []
50
51 #
52 # The ruby network creation expects the list of nodes in the system to be

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75 assoc = options.l1d_assoc,
76 start_index_bit = block_size_bits)
77
78 #
79 # Only one unified L1 cache exists. Can cache instructions and data.
80 #
81 l1_cntrl = L1Cache_Controller(version = i,
82 cntrl_id = cntrl_count,
83 cacheMemory = cache)
83 cacheMemory = cache,
84 ruby_system = ruby_system)
84
85 cpu_seq = RubySequencer(version = i,
86 icache = cache,
87 dcache = cache,
88 physMemPort = system.physmem.port,
85
86 cpu_seq = RubySequencer(version = i,
87 icache = cache,
88 dcache = cache,
89 physMemPort = system.physmem.port,
89 physmem = system.physmem)
90 physmem = system.physmem,
91 ruby_system = ruby_system)
90
91 l1_cntrl.sequencer = cpu_seq
92
93 if piobus != None:
94 cpu_seq.pio_port = piobus.port
95
96 exec("system.l1_cntrl%d = l1_cntrl" % i)
97 #

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120 cntrl_id = cntrl_count,
121 directory = \
122 RubyDirectoryMemory( \
123 version = i,
124 size = dir_size,
125 use_map = options.use_map,
126 map_levels = \
127 options.map_levels),
92
93 l1_cntrl.sequencer = cpu_seq
94
95 if piobus != None:
96 cpu_seq.pio_port = piobus.port
97
98 exec("system.l1_cntrl%d = l1_cntrl" % i)
99 #

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122 cntrl_id = cntrl_count,
123 directory = \
124 RubyDirectoryMemory( \
125 version = i,
126 size = dir_size,
127 use_map = options.use_map,
128 map_levels = \
129 options.map_levels),
128 memBuffer = mem_cntrl)
130 memBuffer = mem_cntrl,
131 ruby_system = ruby_system)
129
130 exec("system.dir_cntrl%d = dir_cntrl" % i)
131 dir_cntrl_nodes.append(dir_cntrl)
132
133 cntrl_count += 1
134
135 for i, dma_device in enumerate(dma_devices):
136 #

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133 exec("system.dir_cntrl%d = dir_cntrl" % i)
134 dir_cntrl_nodes.append(dir_cntrl)
135
136 cntrl_count += 1
137
138 for i, dma_device in enumerate(dma_devices):
139 #

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