MI_example.py (7544:90c5eb6a5e66) MI_example.py (8180:d8587c913ccf)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 46 unchanged lines hidden (view full) ---

55 l1_cntrl_nodes = []
56 dir_cntrl_nodes = []
57 dma_cntrl_nodes = []
58
59 #
60 # Must create the individual controllers before the network to ensure the
61 # controller constructors are called before the network constructor
62 #
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 46 unchanged lines hidden (view full) ---

55 l1_cntrl_nodes = []
56 dir_cntrl_nodes = []
57 dma_cntrl_nodes = []
58
59 #
60 # Must create the individual controllers before the network to ensure the
61 # controller constructors are called before the network constructor
62 #
63 block_size_bits = int(math.log(options.cacheline_size, 2))
63
64 for i in xrange(options.num_cpus):
65 #
66 # First create the Ruby objects associated with this cpu
67 # Only one cache exists for this protocol, so by default use the L1D
68 # config parameters.
69 #
70 cache = Cache(size = options.l1d_size,
64
65 for i in xrange(options.num_cpus):
66 #
67 # First create the Ruby objects associated with this cpu
68 # Only one cache exists for this protocol, so by default use the L1D
69 # config parameters.
70 #
71 cache = Cache(size = options.l1d_size,
71 assoc = options.l1d_assoc)
72 assoc = options.l1d_assoc,
73 start_index_bit = block_size_bits)
72
73 #
74 # Only one unified L1 cache exists. Can cache instructions and data.
75 #
76 cpu_seq = RubySequencer(version = i,
77 icache = cache,
78 dcache = cache,
79 physMemPort = system.physmem.port,

--- 65 unchanged lines hidden --- 		74
75 #
76 # Only one unified L1 cache exists. Can cache instructions and data.
77 #
78 cpu_seq = RubySequencer(version = i,
79 icache = cache,
80 dcache = cache,
81 physMemPort = system.physmem.port,

--- 65 unchanged lines hidden ---