MI_example.py (7538:5691b9dd51f4) | MI_example.py (7541:1e1f63dfd130) |
---|---|
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 26 unchanged lines hidden (view full) --- 35# Note: the cache latency is only used by the sequencer on fast path hits 36# 37class Cache(RubyCache): 38 latency = 3 39 40def define_options(parser): 41 return 42 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 26 unchanged lines hidden (view full) --- 35# Note: the cache latency is only used by the sequencer on fast path hits 36# 37class Cache(RubyCache): 38 latency = 3 39 40def define_options(parser): 41 return 42 |
43def create_system(options, phys_mem, piobus, dma_devices): | 43def create_system(options, system, piobus, dma_devices): |
44 45 if buildEnv['PROTOCOL'] != 'MI_example': 46 panic("This script requires the MI_example protocol to be built.") 47 48 cpu_sequencers = [] 49 50 # 51 # The ruby network creation expects the list of nodes in the system to be --- 19 unchanged lines hidden (view full) --- 71 assoc = options.l1d_assoc) 72 73 # 74 # Only one unified L1 cache exists. Can cache instructions and data. 75 # 76 cpu_seq = RubySequencer(version = i, 77 icache = cache, 78 dcache = cache, | 44 45 if buildEnv['PROTOCOL'] != 'MI_example': 46 panic("This script requires the MI_example protocol to be built.") 47 48 cpu_sequencers = [] 49 50 # 51 # The ruby network creation expects the list of nodes in the system to be --- 19 unchanged lines hidden (view full) --- 71 assoc = options.l1d_assoc) 72 73 # 74 # Only one unified L1 cache exists. Can cache instructions and data. 75 # 76 cpu_seq = RubySequencer(version = i, 77 icache = cache, 78 dcache = cache, |
79 physMemPort = phys_mem.port, 80 physmem = phys_mem) | 79 physMemPort = system.physmem.port, 80 physmem = system.physmem) |
81 82 if piobus != None: 83 cpu_seq.pio_port = piobus.port 84 85 l1_cntrl = L1Cache_Controller(version = i, 86 sequencer = cpu_seq, 87 cacheMemory = cache) | 81 82 if piobus != None: 83 cpu_seq.pio_port = piobus.port 84 85 l1_cntrl = L1Cache_Controller(version = i, 86 sequencer = cpu_seq, 87 cacheMemory = cache) |
88 89 exec("system.l1_cntrl%d = l1_cntrl" % i) |
|
88 # 89 # Add controllers and sequencers to the appropriate lists 90 # 91 cpu_sequencers.append(cpu_seq) 92 l1_cntrl_nodes.append(l1_cntrl) 93 | 90 # 91 # Add controllers and sequencers to the appropriate lists 92 # 93 cpu_sequencers.append(cpu_seq) 94 l1_cntrl_nodes.append(l1_cntrl) 95 |
94 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1 | 96 phys_mem_size = long(system.physmem.range.second) - \ 97 long(system.physmem.range.first) + 1 |
95 mem_module_size = phys_mem_size / options.num_dirs 96 97 for i in xrange(options.num_dirs): 98 # 99 # Create the Ruby objects associated with the directory controller 100 # 101 102 mem_cntrl = RubyMemoryControl(version = i) 103 104 dir_size = MemorySize('0B') 105 dir_size.value = mem_module_size 106 107 dir_cntrl = Directory_Controller(version = i, 108 directory = \ | 98 mem_module_size = phys_mem_size / options.num_dirs 99 100 for i in xrange(options.num_dirs): 101 # 102 # Create the Ruby objects associated with the directory controller 103 # 104 105 mem_cntrl = RubyMemoryControl(version = i) 106 107 dir_size = MemorySize('0B') 108 dir_size.value = mem_module_size 109 110 dir_cntrl = Directory_Controller(version = i, 111 directory = \ |
109 RubyDirectoryMemory(version = i, 110 size = dir_size, 111 use_map = options.use_map, 112 map_levels = options.map_levels), | 112 RubyDirectoryMemory( \ 113 version = i, 114 size = dir_size, 115 use_map = options.use_map, 116 map_levels = \ 117 options.map_levels), |
113 memBuffer = mem_cntrl) 114 | 118 memBuffer = mem_cntrl) 119 |
120 exec("system.dir_cntrl%d = dir_cntrl" % i) |
|
115 dir_cntrl_nodes.append(dir_cntrl) 116 117 for i, dma_device in enumerate(dma_devices): 118 # 119 # Create the Ruby objects associated with the dma controller 120 # 121 dma_seq = DMASequencer(version = i, | 121 dir_cntrl_nodes.append(dir_cntrl) 122 123 for i, dma_device in enumerate(dma_devices): 124 # 125 # Create the Ruby objects associated with the dma controller 126 # 127 dma_seq = DMASequencer(version = i, |
122 physMemPort = phys_mem.port, 123 physmem = phys_mem) | 128 physMemPort = system.physmem.port, 129 physmem = system.physmem) |
124 125 dma_cntrl = DMA_Controller(version = i, 126 dma_sequencer = dma_seq) 127 | 130 131 dma_cntrl = DMA_Controller(version = i, 132 dma_sequencer = dma_seq) 133 |
134 exec("system.dma_cntrl%d = dma_cntrl" % i) |
|
128 dma_cntrl.dma_sequencer.port = dma_device.dma 129 dma_cntrl_nodes.append(dma_cntrl) 130 131 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 132 133 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 135 dma_cntrl.dma_sequencer.port = dma_device.dma 136 dma_cntrl_nodes.append(dma_cntrl) 137 138 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 139 140 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |