MI_example.py (6906:35da51c349e2) MI_example.py (7015:6c91d41dfc12)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 57 unchanged lines hidden (view full) ---

66 # config parameters.
67 #
68 cache = Cache(size = options.l1d_size,
69 assoc = options.l1d_assoc)
70
71 #
72 # Only one unified L1 cache exists. Can cache instructions and data.
73 #
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 57 unchanged lines hidden (view full) ---

66 # config parameters.
67 #
68 cache = Cache(size = options.l1d_size,
69 assoc = options.l1d_assoc)
70
71 #
72 # Only one unified L1 cache exists. Can cache instructions and data.
73 #
74 cpu_seq = RubySequencer(icache = cache,
74 cpu_seq = RubySequencer(version = i,
75 icache = cache,
75 dcache = cache,
76 physMemPort = phys_mem.port,
77 physmem = phys_mem)
78
79 if piobus != None:
80 cpu_seq.pio_port = piobus.port
81
82 l1_cntrl = L1Cache_Controller(version = i,

--- 46 unchanged lines hidden --- 		76 dcache = cache,
77 physMemPort = phys_mem.port,
78 physmem = phys_mem)
79
80 if piobus != None:
81 cpu_seq.pio_port = piobus.port
82
83 l1_cntrl = L1Cache_Controller(version = i,

--- 46 unchanged lines hidden ---