MI_example.py (12598:b80b2d9a251b) | MI_example.py (12976:125099a94768) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 113 unchanged lines hidden (view full) --- 122 # Run each of the ruby memory controllers at a ratio of the frequency of 123 # the ruby system. 124 # clk_divider value is a fix to pass regression. 125 ruby_system.memctrl_clk_domain = DerivedClockDomain( 126 clk_domain=ruby_system.clk_domain, 127 clk_divider=3) 128 129 mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 113 unchanged lines hidden (view full) --- 122 # Run each of the ruby memory controllers at a ratio of the frequency of 123 # the ruby system. 124 # clk_divider value is a fix to pass regression. 125 ruby_system.memctrl_clk_domain = DerivedClockDomain( 126 clk_domain=ruby_system.clk_domain, 127 clk_divider=3) 128 129 mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( |
130 options, system.mem_ranges, bootmem, ruby_system, system) | 130 options, bootmem, ruby_system, system) |
131 dir_cntrl_nodes = mem_dir_cntrl_nodes[:] 132 if rom_dir_cntrl_node is not None: 133 dir_cntrl_nodes.append(rom_dir_cntrl_node) 134 for dir_cntrl in dir_cntrl_nodes: 135 # Connect the directory controllers and the network 136 dir_cntrl.requestToDir = MessageBuffer(ordered = True) 137 dir_cntrl.requestToDir.slave = ruby_system.network.master 138 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) --- 57 unchanged lines hidden --- | 131 dir_cntrl_nodes = mem_dir_cntrl_nodes[:] 132 if rom_dir_cntrl_node is not None: 133 dir_cntrl_nodes.append(rom_dir_cntrl_node) 134 for dir_cntrl in dir_cntrl_nodes: 135 # Connect the directory controllers and the network 136 dir_cntrl.requestToDir = MessageBuffer(ordered = True) 137 dir_cntrl.requestToDir.slave = ruby_system.network.master 138 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) --- 57 unchanged lines hidden --- |