MI_example.py (11065:37e19af67f62) MI_example.py (11266:452e10b868ea)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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69 # First create the Ruby objects associated with this cpu
70 # Only one cache exists for this protocol, so by default use the L1D
71 # config parameters.
72 #
73 cache = L1Cache(size = options.l1d_size,
74 assoc = options.l1d_assoc,
75 start_index_bit = block_size_bits)
76
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 60 unchanged lines hidden (view full) ---

69 # First create the Ruby objects associated with this cpu
70 # Only one cache exists for this protocol, so by default use the L1D
71 # config parameters.
72 #
73 cache = L1Cache(size = options.l1d_size,
74 assoc = options.l1d_assoc,
75 start_index_bit = block_size_bits)
76
77 #
78 # Only one unified L1 cache exists. Can cache instructions and data.
79 #
80 l1_cntrl = L1Cache_Controller(version = i,
81 cacheMemory = cache,
82 send_evictions = send_evicts(options),
83 transitions_per_cycle = options.ports,
84 clk_domain=system.cpu[i].clk_domain,
85 ruby_system = ruby_system)
86
77
87 cpu_seq = RubySequencer(version = i,
88 icache = cache,
89 dcache = cache,
90 clk_domain=system.cpu[i].clk_domain,
91 ruby_system = ruby_system)
78 # the ruby random tester reuses num_cpus to specify the
79 # number of cpu ports connected to the tester object, which
80 # is stored in system.cpu. because there is only ever one
81 # tester object, num_cpus is not necessarily equal to the
82 # size of system.cpu; therefore if len(system.cpu) == 1
83 # we use system.cpu[0] to set the clk_domain, thereby ensuring
84 # we don't index off the end of the cpu list.
85 if len(system.cpu) == 1:
86 clk_domain = system.cpu[0].clk_domain
87 else:
88 clk_domain = system.cpu[i].clk_domain
92
89
90 # Only one unified L1 cache exists. Can cache instructions and data.
91 l1_cntrl = L1Cache_Controller(version=i, cacheMemory=cache,
92 send_evictions=send_evicts(options),
93 transitions_per_cycle=options.ports,
94 clk_domain=clk_domain,
95 ruby_system=ruby_system)
96
97 cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
98 clk_domain=clk_domain, ruby_system=ruby_system)
99
93 l1_cntrl.sequencer = cpu_seq
94 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
95
96 # Add controllers and sequencers to the appropriate lists
97 cpu_sequencers.append(cpu_seq)
98 l1_cntrl_nodes.append(l1_cntrl)
99
100 # Connect the L1 controllers and the network

--- 94 unchanged lines hidden --- 		100 l1_cntrl.sequencer = cpu_seq
101 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
102
103 # Add controllers and sequencers to the appropriate lists
104 cpu_sequencers.append(cpu_seq)
105 l1_cntrl_nodes.append(l1_cntrl)
106
107 # Connect the L1 controllers and the network

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